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Use this WWW form to submit your assignment. You may submit your assignment as many times as you wish; when the submission deadline is reached, your last recorded submission will be the one counted by the TA for grading. Note that each question is tagged with the course outcome(s) it addresses. Your email address is. Your password is. For this question, check all that apply. Which of the following statements is/are true? Allowing a few simultaneous writers to a bus is easy DRAM usually takes less power per bit held than SRAM A multiplexor can be built using a decoder and tri-state drivers The MFC signal indicates no space is left in main memory (memory full capacity) Zin only makes sense in a state where the ALU is doing something (e.g., ALU add) Given this processor hardware design, add control states to the following lo implement an AND-with-immediate instruction (as decoded by the when below), such that andi $rt, $rs, immed yields rt=(rs&immed;). This is actually a MIPS instruction, as we'll discuss later. Given this processor hardware design. add control slates to the following to implement a "fortytwo" instruction (as decoded by the when below), such that fortytwo immed($rs) places the value forty-two in memory, i.e., mem[rs + immed] = 42;. You should add initial values and test your design using the simulator before submitting it here.

Explanation / Answer

1.

Allowing a few simultaneous readers from a bus is easy

DRAM usually takes less power per bit held than SRAM

A multiplexor can be built using a decoder and tri-state drivers

2.

when (op()) {addi} Addi
when (op()) {andi} Andi

Start:
PCout, MARin, MEMread, Yin
CONST(4), ALUadd, Zin, UNTILmfc
MDRout, IRin
Zout, PCin, JUMPonop
HALT /* Should end here on undecoded op */

Addi:
SELrs, REGout, Yin
IRimmedout, ALUadd, Zin
Zout, SELrt, REGin, JUMP(Start)

Andi:
SELrs, REGout, Yin
IRimmedout, ALUand, Zin
Zout, SELrt, REGin, JUMP(Start)

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