can you please write the test bench for this VHDL library IEEE; use IEEE.STD_LOG

Question

can you please write the test bench for this VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.all;   
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity ff is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR(3 downto 0)
);
end ff;

architecture beh of ff is
begin

counting : process (clk,reset) is
variable m : std_logic_vector (3 downto 0) := "0000";
begin
if (reset='1') then
m := "0000";
elsif (rising_edge (clk)) then
m := m + 1;
end if;
dout <= m;
end process;

end beh;

Explanation / Answer

Designing with VHDL • Overview of the Hardware Description Languages (HDL) • VHDL for synthesis – Signals, types, vectors, hierarchy, attributes – Combinational circuits – concurrent vs. sequential assignments – Examples – Mathematical operations, packages – Sequential circuits – DFFs and latches – More examples – State machines – Error protection and error correction © V. Angelov VHDL-FPGA@PI 2013 3 Overview HDL – ABEL, AHDL, Verilog • ABEL – Originally developed for SPLDs and still in use for SPLDs – Now owned by Xilinx • AHDL – Developed by Altera, still used in Altera library components – Syntax similar to Ada • Verilog HDL – Together with VHDL the standard HDL now – Syntax similar to C • Other SystemC, SystemVerilog, Verilog-AMS

Describing a Design

In VHDL an entity is used to describe a hardware module. An entity can be described using,

Let’s see what are these?

Entity Declaration

It defines the names, input output signals and modes of a hardware module.

Syntax

An entity declaration should start with ‘entity’ and end with ‘end’ keywords. The direction will be input, output or inout.

Architecture

Architecture can be described using structural, dataflow, behavioral or mixed style.

Syntax

Here, we should specify the entity name for which we are writing the architecture body. The architecture statements should be inside the ‘begin’ and ‘énd’ keyword. Architecture declarative part may contain variables, constants, or component declaration.

Data Flow Modeling

In this modeling style, the flow of data through the entity is expressed using concurrent (parallel) signal. The concurrent statements in VHDL are WHEN and GENERATE.

Besides them, assignments using only operators (AND, NOT, +, *, sll, etc.) can also be used to construct code.

Finally, a special kind of assignment, called BLOCK, can also be employed in this kind of code.

In concurrent code, the following can be used

In Port can be read Out Port can be written Inout Port can be read and written Buffer Port can be read and written, it can have only one source.

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