Can someone help with this VHDL program? You should try to use only the synthesi

Question

Can someone help with this VHDL program? You should try to use only the synthesizable features of VHDL. In particular, only one "wait" statement is allowed in a process. The "wait for" statements are not allowed in your implementation, but might be used in your test benches.

Problem 2 Develop a behavioral VHDL model for a x-bit, l-to-2 de-multiplexer, r and y being two parameters. Your device should include an ENABLE signal as well as normal inputs and outputs. Develop a test bench for your VHDL de-multiplexer model that demonstrates basic functionality. Simulate your design with one specific set of (x.y) and demonstrate correctness for all possible permutations of inputs other than the words

Explanation / Answer

library IEEE; use IEEE.STD_LOGIC_1164.all; entity demux_1to4 is port( F : in STD_LOGIC; S0,S1: in STD_LOGIC; A,B,C,D: out STD_LOGIC ); end demux_1to4; architecture bhv of demux_1to4 is begin process (F,S0,S1) is begin if (S0 ='0' and S1 = '0') then A

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