A) Explain hazards caused by branch instructions in pipeline design. B) Assume R

Question

A) Explain hazards caused by branch instructions in pipeline design. B) Assume RISC pipeline has five stages IF, ID, EX, MEM, and WB. Consider the following program that computes 1 + 2 + ... + 99 + 100. Lw R1, #100//load 100 to R1. Lw R2, #0//load o to R2 Lw R3, #0//load 0 to R3 Loop: Add R2, R2, R3//increase R2 by the value in R3. Add R3, R3, #1//Increase R3 by 1 Sub R1, #1//Decrease R1 by 1 BNEZ R1, LOOP//go to Loop if R1 is not zero Point out the branch hazard, and show how to insert an instruction into the branch delay slot so that the pipeline stalls are reduced.

Explanation / Answer

BNEZ R1, LOOP After execution of this statement only the processor will able to decide wheather loop is taken or not taken.

So in pipeline either to fetch ADD R2, R2, R3 statement whole depends upon this instruction only.

Now suppose Branching Decision is being taken in execution phase i.e 3rd phase of 5 phase pipeline it will cause stall of 2 cycle which in turn (n-1) phase.

Now Delay slots need to enter = no. of cycle pipeline stalled

Delay Slots = 2

Branch Instruction relies on register R1

So instructions which are modifying register R1 can't be used as Delay Slots.

while Instructions

ADD R2, R2, R3

ADD R3, R3, #1

Can be used as delay slots.

MODIFIED INSTRUCTIONS ORDER TO AVOID STALLING IS AS FOLLOW:-

LOOP: SUB R1, #1

BNEZ R1, LOOP

ADD R2, R2, R3

ADD R3, R3, #1

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