Verilog or VHD code Design and construct a synthesizable Finite State Machine an

Question

Verilog or VHD code

Design and construct a synthesizable Finite State Machine and Datapath which computes the greatest common denominator (GCD) of two numbers ( two 4-bit) numbers and output the binary value of the greatest common divisor of those two numbers.

Your design will consist of two components - the controller and the datapath. The controller is to be a pure FSM. The datapath operates based on signals generated by the controller FSM - it should have no independent controlling logic. ((datapath must be constructed structurally))

Use the GCD algorithm to help you with the code

Explanation / Answer

Use the provided GCD entity (gcd.vhd), create a custom circuit that implements the GCD algorithm by using the 1-process FSMD model. This specification must appear in the GCD architecture entitled FSMD. The entity has a go input and done output (revised 2/23) that work as follows. After being reset, the circuit should wait until go becomes 1 (active high), at which point the GCD algorithm should be performed for the given x and y inputs. Upon completion, done should be asserted (active high). Done should remain asserted until the application is started again, which is represented by a 0 on the go signal followed by a 1. In other words, the circuit shouldn’t continuously execute if go is left at 1.
Use the provided testbench (gcd_tb.vhd) to test your architecture. Note that the testbench uses a configuration to specify which gcd architecture is used. When testing the FSMD, make sure the configuration specifies the FSMD architecture. Also, when simulating, making sure to select the configuration TB_CONFIG, and not the actual testbench. FSM+D 1 .

In this step, you will implement a custom circuit that implements the GCD algorithm by using the datapath shown below:   Implement the datapath by creating an entity datapath1 (store it in datapath1.vhd). You must use a structural description that instantiates all of the components shown. Therefore, you will also need a register entity, a 2x1 mux entity, a subtractor entity, and a comparator entity. The register entity must have an enable input that allows/prevents data from being stored. The comparator entity must have a less than output, which connects to the x_lt_y signal, and a not equal output, which connects to the x_ne_y signal. You are free to implement these entities however you like, as long as they have these basic capabilities, and as long as each entity uses a generic for the width. Next, implement a controller entity called ctrl1 (store it in ctrl1.vhd) that uses the control signals for the illustrated datapath to execute the GCD algorithm. Feel free to use either the 1-process or 2-process FSM model (I recommend the 2-process model). For the provided gcd entity implement the structural architecture (FSM_D1) that connects the controller to the datapath. You must use the FSM_D1 architecture. Use the provided testbench (gcd_tb.vhd) to test your architecture. Note that the testbench uses a configuration to specify which gcd architecture is used. When testing the FSM_D1, make sure the configuration specifies the FSM_D1 architecture. Also, when simulating, making sure to select the configuration TB_CONFIG, and not the actual testbench.

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