Verilog language \"code problem\". I know there is some sort of \"always\" state

Question

Verilog language "code problem". I know there is some sort of "always" statement... can't figure out how to finish it. Thanks in advance for the help.

Design a logic module to multiply an 8-bit binary number A [0:7] by a 4-bit binary number N [0:3]. The multiply is started when M is asserted. The output F is asserted when the multiply is completed and the product PI0:15is avilable. The outputs need to remain valid until the next multiply command is given. Assume M is valid for several of your clock cycles and then is de-asserted. Implementthe multiply using repeated addition of A to form parital products. Simulate and verify correct operation of your design. Below is what have so far... Below is whatI have so far.. module numberz (A.N.M.F, P) 1 2 3 input M: input 7:0 A: input t3:0] N: output F: output 115:0 P: 5 6 7 8 9 10 //always(M) //begin assign P-A-N: assignF2: //end 12 13 14 endimodule

Explanation / Answer

i can give solution an 8_bit cannot be directly multiplied to a 4_bit you shoul have both as 8-bit when multiplied

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