Assume that a single-cycle data path is driven by a 70MHz clock and is to be con

Question

Assume that a single-cycle data path is driven by a 70MHz clock and is to be converted into a multi-stage pipelined system. What minimum number of stages would be required by the pipeline to achieve a cycle time of 4ns assuming the logic is evenly distributed among the stages? There is no latch latency. Assume that a single-cycle data path is driven by a 70MHz clock and is to be converted into a multi-stage pipelined system. What minimum number of stages would be required by the pipeline to achieve a cycle time of 4ns assuming the logic is evenly distributed among the stages? There is no latch latency.

Explanation / Answer

Clock frequency = 70 MHz

Therefore,clock time = 1/(70*106) = 1.42 * 10-8 seconds

Given cycle time = 4ns

Therefore, the minimum no of stages required =

=>clock time < (cycle time * N) + time for latency

(as no time for latency and N stands for no of stages)

=> clock time < (cycle time * N)

=>(clock time / cycle time) < N

=>(1.42 * 10-8 ) / (4 * 10-9) < N

=> 3.55 < N

So , the minimum number of stages are 3.55 =~ 4 (Answer)

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