Given a static multiple issue unit for the MIPS where the system can do a arithm

Question

Given a static multiple issue unit for the MIPS where the system can do a arithmetic/branch instruction with one issue slot and a load/store instruction with a second issue slot. The instructions can not be dependent on one another and, if a slot is unable to be filled with and instruction it is filled with a NOP. Give the following code show the contents of the separates slot below. How much of a speedup will you see over a standard single issue unit? lw $r0, 20($r6) add $r0, $r0, $r1 add $r2, $r3, $r4 sw $r0, 24($r6) sw $r1, 28($r6)

Explanation / Answer

This behavior is indicated in the instruction specifications below. For brevity, the function advance_pc (int) is used in many of the instruction descriptions. This function is defined as follows:

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