Given a static multiple issue unit for the MIPS processor where the system can d

Question

Given a static multiple issue unit for the MIPS processor where the system can do a arithmetic/branch instruction with one issue slot and a load/store instruction with a second issue slot. The instructions can not be dependent on one another and, if a slot is unable to be filled with an instruction it is filled with a NOP. Given the following code show the contents of the separate slot below. How much of a speedup will you see over a standard single issue unit? lw $r0, 20($r6) add $r0, $r0, $r1 sw $r1, 28($r6) add $r2, $r3, $r4 sw $r0, 24($r6) Speedup: _____

Explanation / Answer

Here is the explanation:

Since it is multiple issue therefor ADD/BRANCH and LOAD/STORE instruction can take place in one cycle.

Here lw $r0,20($r6) and add $r2,$r3,$r4 can take place in one cycle because none value is dependent.

In the next cycle sw $r1,28($r6) we can store value of $r1 in 28($r6) because meanwhile lw instruction completes then in the next cycle we can take add $r0,$r0,$r1 instruction.

And finally in clock cycle 4 sw $r0 , 24($r6) instruction.

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In multiple issue:-

Total cycles required are 4

Therefore, CPI = 4/5= 0.8

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If there would have been only single issue then :-

So, In single issue :-

Total cycles required are 5

Therefore CPI = 5/5= 1

Hence,

Speedup = CPIold / CPInew = 1/0.8=1.25

Clock Cycle ALU/BRANCH LOAD/STORE 1 add $r2,$r3,$r4 lw $r0,20($r6) 2 NOP sw $r1,28($r6) 3 add $r0,$r0,$r1 NOP 4 NOP sw $r0 , 24($r6) 5 NOP NOP

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