Consider a cache with the following information The cache has a total of 2048 by

Question

Consider a cache with the following information

The cache has a total of 2048 bytes, which are divided into 128 blocks with 16 bytes in each block

The main memory has a total of 65536 bytes, which are divided into 4096 blocks with 16 bytes in each block

The main memory uses byte addressing, and thus a memory address has a total of 16 bits

The cache uses 4-way (i.e., k=4) set-associative mapping and LRU replacement.

The total number of sets in the cache is( ) , and the number of bits in a tag associated with a cache block is ( )

Consider the following five read requests for bytes at the following addresses.

request 1 for the byte at address 0x0210

request 2 for the byte at address 0x0410

request 3 for the byte at address 0x0610

request 4 for the byte at address 0x0810

request 5 for the byte at address 0x0214

request 6 for the byte at address 0x0A10

All of these addresses correspond to cache set 1, and thus we consider only case set 1. Initially, we have the following information for cache set 1

cache

set

cache

block

after executing read request 1, we have

cache

set

cache

block

tag

(binary)

counter

(decimal)

after executing read request 2, we have

cache

set

cache

block

tag

(binary)

counter

(decimal)

after executing read request 3, we have

cache

set

cache

block

tag

(binary)

counter

(decimal)

after executing read request 4, we have

cache

set

cache

block

tag

(binary)

counter

(decimal)

after executing read request 5, we have

cache

set

cache

block

tag

(binary)

counter

(decimal)

after executing read request 6, we have

cache

set

cache

block

tag

(binary)

counter

(decimal)

cache

set

cache

block

Valid tag counter 1 4 0 n/a 0 1 5 0 n/a 0 1 6 0 n/a 0 1 7 0 n/a 0

Explanation / Answer

Cache = 2048 B
No. of Blocks = 128
size of block = 16 B

Main Memory = 65536 B
No. of Blocks = 4096
size of block = 16 B

main memory uses byte addressing, and memory address has 16 bits
cache uses 4-way set-associative mapping and LRU(lease recently used) replacement.
total number of sets in the cache is 7
number of bits in a tag associated with a cache block is 4

Provide details of what is required to calculate.

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