This exercise is intended to help you understand the relationship between forwar

Question

This exercise is intended to help you understand the relationship between forwarding, hazard detection, and ISA design. Problems in this exercise refer to the following sequences of instructions, and assume that it is executed on a 5-stagc pipelined datapath: a. ADD R5.R2.Rl LW R3,4(R5) LW R2.0(R2) OR R3,R5,R3 SW R3,0(R5) b. LWR2,0(R1) AND RI,R2,Rl LW R3,0(R2) LW Rl,0(R1) SW R1,0(R2) If there is no forwarding or hazard detection, insert NOPs to ensure correct execution. Repeat 4.21.1 but now use NOPs only when a hazard cannot be avoided by changing or rearranging these instructions. You can assume register R7 can be used to hold temporary' values in your modified code. If the processor has forwarding, but we forgot to implement the hazard detection unit, what happens when this code executes? If there is forwarding, for the first five cycles during the execution of this code, specify which signals are asserted in each cycle by hazard detection and forwarding units in Figure 4.60. If there is no forwarding, what new' inputs and output signals do we need for the hazard detection unit in Figure 4.60? Using this instruction sequence as an example, explain why each signal is needed. For the new hazard detection unit from 4.21.5, specify which output signals it asserts in each of the first five cycles during the execution of this code.

Explanation / Answer

4.21.1.

aAns:// lw $1,40($6)
nop
nop
add $2,$3,$1
add $1,$6,$4
nop
sw $2,20($4)
add $1,$1,$4 //

bAns. // add $1,$5,$3
nop
nop
sw $1,0($2)
lw $1,4($2)
nop
nop
add $5,$5,$1
sw $1,0($2) //

4.21.2: We can move up an instruction by swapping its place with another instruction
that has no dependences with it, so we can try to fi ll some nop slots with such
instructions. so use "R7" to eliminate ""WAW / WAR"" dependences so that we can
have "more" -instructions to move_up.

a. //I1: lw $7,40($6) Produce $7 instead of $1
I3: add $1,$6,$4 Moved up to fi ll NOP slot
nop
I2: add $2,$3,$7 Use "$7" instead of "$1"
I5: and $1,$1,$4 Movedd upto fill "NOP" slot
nop
I4: sw $2,20($4) //

b. // I1: add $7,$5,$3 Produce "$7" instead of "$1"
I3: lw $1,4($2) Moved upto fill "NOP" slot
nop
I2: sw $7,0($2) Usee "$7" instead of "$1"
I4: add $5,$5,$1
I5: sw $1,0($2) //

4.21.2::With 'forwarding'., "the hazard_detection_unit" is still needed because as it must
'insert' a "one-cycle" stall whenever the 'load' supplies value to instruction that
'immediately' follows that 'load'. Without the 'hazard-detection-unit'.., the 'instruction'
that depends on the immediately 'preceding' load gets the stale_value the 'register' had
before the 'load_instruction'.
1. // 'I2' gets the value of '$1' from before 'I1'., not from 'I1' as it should.//
2. // 'I4' gets the value of '$1' from 'I1', not from 'I3' as it should. //

4.21.4::The 'outputs' of "hazard_detection_unit" are 'PC_Write', IF//IDWrite, &
'ID/EXZero' .Note that "IF/IDWrite" is always equal to 'PCWrite'., & 'ED/ExZero' is always the 'opposite'
of 'PCWrite'.. So that we can only show the value of "PCWrite" for each_cycle.The
'outputs' of forwarding_unit is 'ALUin1' & 'ALUin2'., which control 'Muxes 'which
select the 'first' and 'second' input of the "ALU". The 3 possible values for -ALUin1
or ALUin2 are 0--no_forwarding, 1 --forward 'ALU' output from previous instruction,
or 2--forward data value for 2nd-previous instruction. We have the..,

Instruction sequence    First five cycles   Signals   1 2 3 4 5

a. lw $1,40($6)   IF ID EX MEM WB 1: PCWrite = 1, ALUin1 = X, ALUin2 = X
add $2,$3,$1    IF ID *** EX   2: PCWrite = 1, ALUin1 = X, ALUin2 = X
add $1,$6,$4    IF *** ID 3: PCWrite = 1, ALUin1 = 0, ALUin2 = 0
sw $2,20($4) IF 4: PCWrite = 0, ALUin1 = X, ALUin2 = X
and $1,$1,$4   5: PCWrite = 1, ALUin1 = 0, ALUin2 = 2

b. add $1,$5,$3   IF ID EX MEM WB   1: PCWrite = 1, ALUin1 = X, ALUin2 = X
sw $1,0($2) IF ID EX MEM 2: PCWrite = 1, ALUin1 = X, ALUin2 = X
lw $1,4($2)   IF ID EX 3: PCWrite = 1, ALUin1 = 0, ALUin2 = 0
add $5,$5,$1 IF ID   4: PCWrite = 1, ALUin1 = 0, ALUin2 = 1
sw $1,0($2) IF   5: PCWrite = 1, ALUin1 = 0, ALUin2 = 0

4.21.5 The ' iinstruction ' that is currently in the ' ID-stage ' needs to 'stalled' if it
depends on the value-producd by instruction in 'EX' or the instructin in the
'MEM-stage'. So we have to 'check' the '' destination_registr '' of these 2 instructions.
-->For the instruction in the '' EX_stage ''., we have to check 'Rd' for ''R_type'' instructions
& ' Rd ' for -loads. -->For the instruction in "MEM-stage"., the 'destination_register'
is already selected "" by the Mux in EX_stage ""., so we have to check that 'register'
'number'.
-->The additionl_inputs to "hazard _detection_unit" are register 'Rd' from the 'ID/EX'
pipelne_register & output no.of the o/p register from the ""EX/MEM""
pipeline_registr. --> The "Rt" field from '' ID/EX '' register is already an "input" of the
"hazard_detectio_ unit".
-->No additional 'outputs' are neededd.. We can 'stall' the 'pipeline'' using the 3 'output'
signals that we 'have'.

4.21.6.

In '4.21.5' it is explained and, we should only need to specify the value of the "PCWrite"
signal, because of "IF/IDWrite" is equal to "PCWrite" and the "ID/EXzero" signal is its
''opposite''.
//

Instruction_sequence   First five cycles Signals   1 2 3 4 5
a. lw $1,40($6)   IF ID EX MEM WB 1: PCWrite = 1
add $2,$3,$1 IF ID *** ***   2: PCWrite = 1   
add $1,$6,$4   IF *** ***   3: PCWrite = 1
sw $2,20($4) *** 4: PCWrite = 0
and $1,$1,$4   5: PCWrite = 0

b. add $1,$5,$3 IF ID EX MEM WB 1: PCWrite = 1   sw $1,0($2)     IF ID *** ***   2: PCWrite = 1 lw $1,4($2) IF *** *** 3: PCWrite = 1 add $5,$5,$1   *** 4. PCWrite = 0 sw $1,0($2)   5: PCWrite = 0

// // thank you //

Related Questions

Navigate

• Browse (All)
• Browse T
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.