Consider a processor with the following features: 35% of the instructions are da

Question

Consider a processor with the following features: 35% of the instructions are data moving instructions (LW/SW etc.) L1 cache hit time: 0.96ns, L1 cache miss rate: 11% For those that miss from L1 cache, an L2 cache will be accessed: L2 cache access time: 3.22ns, L2 cache miss rate: 60% For those that miss from L2 cache, L2 miss penalty/main memory access time: 80ns a. Assume that the L1 hit time determines the clock cycle time. What is the clock rate for this processor? b. What is the AMAT for this processor? c. Assuming a base CPI of 1.0 without any memory stalls, what is the actual CPI considering the delay caused by data memory accesses?

Explanation / Answer

Solution:

a)

So L1 cache hit time is 0.96 ns and if L1 cache is determining the clock rate then

clock rate= 1/0.96*10^9= 1.04167 Ghz

b)

So miss rate for L1= 11%, this means that hit rate= 89% and access time= 0.96 ns

Similarly for Ll2 Hit rate= 40% and access time= 3.22ns

Main memory access time= 80 ns

Average memory access time (AMAT)= L1 hit rate*L1 memory access time+(L1 miss rate*(L2 hit rate*L2 memory access time*(L2 miss rate*(main memory access time))))

= (0.89*0.96)+(0.11*((3.22*0.4)*(0.6*(80)))= 7.65504 ns

c)

So 35% of the time is taken by memory access and without that CPI is 1, which means that in 65% of the processor is taking 1 CPI so 35% wil take= 35*(1/65)= 0.53846153846 CPI

and total CPI will be 1.0.53846153846.

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