One. Match the terms below with the explanations which follow. DO NOT DRAW LINES
ID: 3829625 • Letter: O
Question
One. Match the terms below with the explanations which follow. DO NOT DRAW LINES.
(a) cache hit
(b) cache line fill
(c) write hit
___ The processor attempts to write an operand to a cacheable area of memory, and a valid cache line exists for that memory address, the processor can write into the cache instead of writing it to system memory.
___ The memory location containing that operand is still cached the next time the processor attempts to access the operand, and the processor can read the operand from the cache instead of going back to memory.
___ When the processor recognizes that an operand being read from memory is cacheable, the processor reads an entire cache line into the appropriate cache.
Two. The procedure when one processor (A) attempts to find out if another processor (B) has cached a memory location which A requires is called:
a. data coherency check c. snooping
b. read misses d. write hits
Three. IA-32 and Intel 64 processors use the MESI (modified, exclusive, shared, invalid) cache protocol to maintain consistency with internal caches and caches in other processors (see Section 11.4, “Cache Control Protocol”, in Volume 3).
(circle) In which of the MESI states (modified, exclusive, shared, invalid) can a cache line also be present in another processor's cache?
Four. Refer to the instruction descriptions in Volume 2. Which instructions move data into level 1 cache?
Five. Refer to page 86 of the course text, under the heading “Sixth Optimization…”. Answer Question 2.11 (a) on page 138 in the course text.
With: _______ Without: ________
Show your work on the back page.
Explanation / Answer
1. When the processor recognizes that an operand being read from memory is cacheable, the processor reads an
entire cache line into the appropriate cache (L1, L2, L3, or all). This operation is called a cache LINE FILL.
If the memory location containing that operand is still cached the next time the processor attempts to access the
operand, the processor can read the operand from the cache instead of going back to memory. This operation is
called a CACHE HIT.
When the processor attempts to write an operand to a cacheable area of memory, it first checks if a cache line for
that memory location exists in the cache. If a valid cache line does exist, the processor (depending on the write
policy currently in force) can write the operand into the cache instead of writing it out to system memory. This
operation is called a WRITE HIT.
2. c: snooping - Also referred to as a bus-snooping protocol, a protocol for maintaining cache coherency in symmetric multiprocessing environments. In a snooping system, all caches on the bus monitor (or snoop) the bus to determine if they have a copy of the block of data that is requested on the bus.
3. Shared - Indicates that this cache line may be stored in other caches of the machine and is clean - it matches the main memory. The line may be discarded (changed to the Invalid state) at any time.
4. More information needed
5. More information needed
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