8. In the operation of the Intel Core each instruction is translated into one or
ID: 3830185 • Letter: 8
Question
8. In the operation of the Intel Core each instruction is translated into one or more fixed-length RISC instructions known as _________.
9. The ________ protects critical data used by the operating systemfrom user applications, separating processing tasks by disallowing accessto each other’s data, disabling access to memory regions, allowing memoryregions to be defined as read-only, and detecting unexpected memory accessesthat could potentially break the system.
10. The _________ predicts the instruction stream, fetches instructions from the L1 instruction cache, and places the fetched instructions into a buffer for consumption by the decode pipeline.
11. Instruction-level parallelism is also determined by __________, which is the time until the result of an instruction is available for use as an operand in a subsequent instruction.
12. Superscalar instruction issue policies are grouped into the following categories: in-order issue with in-order completion, out-of-order issue with out-of-order completion, and ____________.
13. With ____________ any number of instructions may be in the execution stage at any one time, up to the maximum degree of machine parallelism across all functional units.
14. The ________ is a buffer used to decouple the decode and execute stages of the pipeline to allow out-of-order issue.
15. An alternative to _________ is a scoreboarding.
Explanation / Answer
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Answer 8) 32-bit instructions
Answer 9) Memory Protection Unit (MPU)
Answer10) Instruction Fetch Unit
Answer 11) operation latency
Answer12) in-order issue with out-of-order completion
Answer13) out-of-order completion
Answer 14) instruction window
Answer 15) the Tomasulo's scheme
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