What is wrong? Xilinx Design Tools ISE Design Suite 14.7 timescale 1ns / 1ps ///
ID: 3834179 • Letter: W
Question
What is wrong?
Xilinx Design Tools
ISE Design Suite 14.7
timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:31:45 04/28/2017
// Design Name:
// Module Name: Final
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Final2(insert25, lid_close, bw, nw, hw, ssd, Rssd, clk, ld);
input insert25;
input lid_close;
input bw;
input nw;
input hw;
output ld;
output [6:0] Rssd,ssd;
reg [6:0] Rssd,ssd;
input clk;
reg [2:0] ld;
reg[1:0] state, nxt_state;
parameter state0 = 0, state1 =1, state2=2, state3=3, state4=4, state5=5,state6=6, state7=7;
reg bc=0;
reg no=0;
reg Hy=0;
reg done = 0;
integer countm = 0;
integer distempL, distempR;
integer cost = 0;
reg disp_id = 0;
// Case when bw is selected.
always@(posedge bw)
begin
if(countm >= 50)
begin
if (lid_close == 1)
begin
bc = 1;
done =1;
distempL = 2;
distempR = 5;
cost = 50;
end
end
end
// case when nO is selected
always@ (posedge nw)
begin
if (countm >= 75)
begin
if (lid_close == 1)
begin
no = 1;
done = 1;
distempL = 2;
distempR = 5;
cost = 75;
end
end
end
// Case when HY is selected
always@ (posedge hw)
begin
if (countm >= 100)
begin
if (lid_close == 1)
Hy = 1;
done =1;
distempL = 2;
distempR = 5;
cost = 100;
end
end
// Case when btn is pressed
always@ (posedge insert25)
begin
if(countm == 0)
begin
countm = 25;
distempL = 2;
distempR = 5;
end
if (countm == 25)
begin
countm = 50;
distempL = 5;
distempR = 0;
end
if (countm == 50)
begin
countm = 75;
distempL = 7;
distempR = 5;
end
if (countm == 75)
begin
countm = 100;
distempL = 1;
distempR = 0;
end
else
$display("Invalid");
end
// Left display
always@ (distempL)
begin
case(distempL)
1: ssd = 7'b0110000;
2: ssd = 7'b1101101;
5: ssd = 7'b1011011;
7: ssd = 7'b1110000;
default: ssd = 7'b1111110;
endcase
end
// Right display
always@ (distempR)
begin
case (distempR)
1'd0: Rssd = 7'b1111110;
1'd5: Rssd = 7'b1011011;
default: Rssd = 7'b1111110;
endcase
end
always@(posedge clk)
begin
state = nxt_state;
end
// Status states for wash
always@ (state)
begin
case (state)
state0: ld = 3'b100;
state1: ld = 3'b101;
state2: ld = 3'b100;
state3: ld = 3'b101;
state4: ld = 3'b010;
state5: ld = 3'b011;
state6: ld = 3'b001;
state7: ld = 3'b000;
default : ld = 3'b000; //default off
endcase
end
always@(state)
begin
case(state)
state0:
if (bc) nxt_state = state1;
else if (no) nxt_state = state1;
else if (Hy) nxt_state = state1;
state1:
if (bc) nxt_state = state5;
else if (no) nxt_state = state4;
else if (Hy) nxt_state = state2;
state2:
if(Hy) nxt_state = state3;
state3:
if(Hy) nxt_state = state4;
state4:
if (no) nxt_state = state5;
else if (Hy) nxt_state = state5;
state5:
if (bc) nxt_state = state6;
else if (no) nxt_state = state6;
else if (Hy) nxt_state = state6;
state6:
if (bc) nxt_state = state7;
else if (no) nxt_state = state7;
else if (Hy) nxt_state = state7;
default nxt_state = state0;
endcase
end
always@(negedge done)
begin
countm = countm - cost;
bc =0;
Hy =0;
no = 0;
end
endmodule
Explanation / Answer
module addbit ( 2 a , // first input 3 b , // Second input 4 ci , // Carry input 5 sum , // sum output 6 co // carry output 7 ); 8 //Input declaration 9 input a; 10 input b; 11 input ci; 12 //Ouput declaration 13 output sum; 14 output co; 15 //Port Data types 16 wire a; 17 wire b; 18 wire ci; 19 wire sum; 20 wire co; 21 //Code starts here 22 assign {co,sum} = a + b + ci; 23 24 endmodule // End of Module addbit
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