Loop: iw sto, 8 write Upper input into implementation give file. value the pts 1

ID: 3836329 • Letter: L

Question

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Explanation / Answer

A single-cycle datapath executes in one cycle all instructions that the datapath is designed to implement. This clearly impacts CPI in a beneficial way, namely, CPI = 1 cycle for all instructions. In this section, we first examine the design discipline for implementing such a datapath using the hardware components and instruction-specific datapaths developed.

Single Datapaths :

The key to efficient single-cycle datapath design is to find commonalities among instruction types. For example, the R-format MIPS instruction datapath and the load/store datapath of Figure 4.8 have similar register file and ALU connections. However, the following differences can also be observed:

The second ALU input is a register (R-format instruction) or a signed-extended lower 16 bits of the instruction (e.g., a load/store offset).

The value written to the register file is obtained from the ALU (R-format instruction) or memory (load/store instruction).

These two datapath designs can be combined to include separate instruction and data memory, as shown in Figure. The combination requires an adder and an ALU to respectively increment the PC and execute the R-format instruction.

Adding the branch datapath to the datapath illustrated in Figure 4.9 produces the augmented datapath shown in Figure. The branch instruction uses the main ALU to compare its operands and the adder computes the branch target address. Another multiplexer is required to select either the next instruction address (PC + 4) or the branch target address to be the new value for the PC.

ALU control : The control unit is responsible for setting all the control signals so that each instruction is executed properly.

— The control unit’s input is the 32-bit instruction word.

— The outputs are values for the blue control signals in the datapath.

Most of the signals can be generated from the instruction opcode alone, and not the entire 32-bit word

To illustrate the relevant control signals, we will show the route that is

taken through the datapath by R-type, lw, sw and beq instructions.

R-type instruction path

lw instruction path

sw instruction path

In the figure, ALUop the branch may or may not be taken, depending on the ALU’s Zero output.

Control signal table

Operation

RegDst

RegWrite

ALUSrc

ALUOp

Mem Write

Mem Read

Mem To Reg

Add

010

Sub

110

And

000

001

Slt

111

010

beq

110

Single-Cycle Implementation:

CPI:

The average number of clock cycles per instruction, or CPI, is a function of the machine and program.

Clock cycle time:

One cycle is the minimum time it takes the CPU to do any work.

Generally, a higher frequency is better.

Some examples illustrate some typical frequencies.

— A 500MHz processor has a cycle time of 2ns.

— A 2GHz (2000MHz) CPU has a cycle time of just 0.5ns (500ps).