Help will be rated and thanked. 1.What hardware component does the runtime addre
ID: 3857697 • Letter: H
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Help will be rated and thanked.
1.What hardware component does the runtime address mapping from logical address to physical address ?
A. address cache
B. memory controller
C. processor
E.MMU
2. Consider a CPU with a TLB that caches 1024 page table entries. An access to the TLB takes 500 ps. One access to main memory takes 1000 ps. What is the TLB hit rate such that the effective memory-access time is 1600 ps ?
A.0.9125
B.0.89
C.0.92
D.0.9
3. Swapping in mobile system OS, like Android, is not feasible because: (More than 1)
A. the amount of flash memory on mobile systems is typically small
B. Swapping processes in not a good idea since mobile OSs do not support paging
C. in single-user systems, like smartphones, there is no need to extend the memory space using virtual memory techniques, like swapping and paging
D. repeated write operations on flash memory swap devices could reduce device reliability, leading to failure or memory corruption
4. A computer with an Intel 80386 CPU configured to use the IA-32 memory architecture with segmentation runs an OS that supports dynamic loading with shared libraries. In which segment table are stored the descriptors of the segments associated with the shared libraries ?
A. the page directory
B. trick question ! One cannot devise memory sharing with segmentation only.
C. the PAE base table
D. the Global Descriptor Table
E. The Local Descriptor Table
5. On a particular OS the compiler generates addresses that can be modified at load time, but the program, once loaded, cannot be moved during its execution unless it is reloaded.
What kind of address binding is used ?
A. execution time address binding
B. dynamic address binding
C. load time address binding
D. compile time address binding
6. A computer has a two-level hierarchical page table structure. How many read operations with the physical memory are needed in total to load a variable from main memory to a register considering there is a TLB miss for this operation?
D.adress bus the TL8 hitr es 1024 page Consider a CPU with a TLB that caches 1024 page table entries. An access to the TLB takes 500 ps. One access to main memory takes 1000 ps. What is the TLB hit rate such that the effective memory-access time is 1600 ps? 09125 089 0.92 0.9 6.67 pts Question 11 Swapping in mobile system OS, like Android, is not feasible because: the anount of flesh memory on mbile systers is typically small fesh mer swepping processes in not a pood idea since motile OSs do not support pegire in single-user systems, like smartphones, there is no need to extend the memory space using virtual memory technioues, ike swapping and peging repeated write operations on flash memory swap devices could reduce device reliability, leadirig to failure or memory corruption 6.67 pts Question 12 Inel B0386 CPU coonfngured lo use the 14-32 meory arhitecture with semnan runs an OS hal supports dynamicg with shared libraries In which segent lable are slured the descriplorsof the segirienls associaled with Lhe Acompuler wilh shared libraries? the page directory trick question!One cannor devise memory sharing with segmentatian onty the PAE bne table the Glabal Descriptor lableExplanation / Answer
1.MMU
Explanation: A memory management unit (MMU) some of the time called paged memory management unit (PMMU) is a PC equipment unit having all memory references gone through itself basically playing out the interpretation of virtual memory delivers to physical addresses.It is typically executed as a major aspect of the focal handling unit (CPU) yet it likewise can be as a different incorporated circuit.
3. A and B
Explanation:There are three reasons:
First is that these mobile devices typically use flash memory with limited capacity and swapping is avoided because of this space constraint.
Second flash memory can support a limited number of write operations before it becomes less reliable.
Lastly there is typically poor throughput between mainmemory and flash memory.
4.The page directory
Explanation: The selector is an index into the segment descriptor table.The segment descriptor result plus the original offset is used to produce a linear address with dir/page/offset.The dir is an index into a page directory the entry from this directory selects the page table and the page field is an index into that page table.The entry from the page table plus the offset is the physical address.
5. Option B
Explanation: If the process can be moved during its execution from one memory segment to another, then binding must be delayed until run time.Most-general-purpose operating systems use this method, and special hardware is required
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