library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all ; entity shi
ID: 3862680 • Letter: L
Question
library ieee; use ieee.std_logic_1164.all;
use ieee.numeric_std.all
; entity shiftReg8 is
port ( clk : in std_logic;
rstb : in std_logic;
Din : in std_logic;
shift: in std_logic;
dir: in std_logic;
-- 0 for left, 1 for right bout : out std_logic_vector(7 downto 0) );
end entity;
architecture behavioral of shiftReg8 is
-- -- internal signals
signal bout_sig: std_logic_vector(7 downto 0);
begin
process(clk, rstb)
begin
if (rstb = '0') then bout_sig <= (others => '0');
elsif (rising_edge (clk)) then
if (shift = '0') then bout_sig <= bout_sig;
elsif(dir = '0') then bout_sig <= bout_sig(6 downto 0) & Din;
else bout_sig <= Din & bout_sig(7 downto 1);
end if;
end if;
end process;
bout <= bout_sig;
end behavioral;
Modify the behavioral VHDL code for the L/R shift register to add an additional input amt(A). When A is low, the shift register shifts by 1 spot, when A is high the shift register shifts by 2 spots. Instead of shifting in Din, rotate the contents of the register. Reset should put the register in the 1001 0110 state. Provide code and a simulationExplanation / Answer
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY counter_tb IS
END counter_tb;
ARCHITECTURE behavior OF counter_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ff
PORT(
clk : IN std_logic;
reset : IN std_logic;
dout : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal dout : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 50 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ff PORT MAP (
clk => clk,
reset => reset,
dout => dout
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
reset<='0';
wait for 100 ns;
reset<='0';
wait for 100 ns;
reset<='0';
wait for 100 ns;
reset<='0';
wait for 100 ns;
reset<='0';
wait for 100 ns;
reset<='0';
wait for 100 ns;
reset<='0';
wait for 100 ns;
reset<='0';
wait for 100 ns;
reset<='1';
wait for 100 ns;
reset<='0';
wait for 100 ns;
reset<='0';
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
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