Examine the difficulty of adding a proposed LWI Rd,Rm(Rn)(“LoadWith Increment”)

Question

Examine the difficulty of adding a proposed LWI Rd,Rm(Rn)(“LoadWith Increment”) instruction to LEGv8. Interpretation: Reg[Rd]=Mem[Reg[Rm]+Reg[Rn]]

4.11.1 [5] <§4.4> Which new functional blocks (if any) do we need for this instruction?

4.11.2 [5]<§4.4>Whichexistingfunctionalblocks(ifany)requiremodi cation?

4.11.3 [5]<§4.4>Whichnewdatapaths(ifany)doweneedforthisinstruction?

4.11.4 [5] <§4.4> What new signals do we need (if any) from the control unit to support this instruction?

Explanation / Answer

I have written the Instruction set for the repective Interpretation:-

4.11.1) Let me explain you the process of load with increment which can be done in two ways:-

i) Firstly read port in Registers basically to define read Rn and next by choosing a alternative ALU to add Rn to Rp +
Rq or Finally a third input to the actual ALU,
ii) Last step is to extend the actual ALU to perform the shifts and simultaneously adding the SLL ALU operations.

4.11.2)

i)First of all, The instruction adopts the instruction memory, both actual read ports like ALU, Registers and
the write port.
ii). After that, Make sure one of the actual register read ports have the lane
that reached immediate to the ALU, and the register write port.

4.11.4)
i)In this step, we need to focus more on a controlling of a signal which tells the Arithmetic logic unit to perform the specific task.
ii) Next, This time we need to differenciate the ALU Operations to control signals which adds the SLL modiifcation to it.

Interprepation Set:

ADDI Rs,Ra, Imm12: Reg[Rd] = Reg[Rn].
ADDS Rb, Ra, Rz: Reg[Ra] = Reg[Rs] + Reg[Rb].
B Imm26: PC = PC

B.LT Imm19: PC = PC.

BL Imm26: X30 = PC + 4 , PC = PC

BR Rd: PC = Reg[Rd].

CBZ Rt, Imm19: If (Reg[Rt] == 0) PC = PC

LDUR Rt, [Rn, #Imm9]: Reg[Rt] = Mem[Reg[Rn]

STUR Rt, [Rn, #Imm9]: Mem[Reg[Rn] +
SUBS Rd, Rn, Rm: Reg[Rd] = Reg[Rn] - Reg[Rm].

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