FIGURE 3.10 Division example using the algorithm in Figure 3.9. The bit examined
ID: 3864870 • Letter: F
Question
FIGURE 3.10 Division example using the algorithm in Figure 3.9. The bit examined to determine the next step is circled in color. Divisor 32 bits 32-bit ALU Shift right 7 Control Shift left Remainder Write test 64 bits FIGURE 3.11 An improved version of the division hardware The Divisor register, ALU, and Quotient register are all 32 bits wide, with only the Remainder register left at 64 bits. Compared to Figure the ALU Divisor registers are halved and the remainder is shifted left. This version also the combines Quotient register with the right half of the out of the register. not lost.) 3.5, the Remainder register Figure should really be 65 make sure the carryExplanation / Answer
.section .init
.globl _start
_start:
b main
.section .text
main:
mov sp,#0x8000
ldr r4,=0x20200000
mov r5,#1
lsl r5,#18
str r5,[r4,#4]
mov r5,#1
lsl r5,#16
mov r7,#0x00000500 /*the 'on delay'*/
mov r8,#0x00000050 /*the 'off delay'*/
mov r9,#0x00000500
outerLoop$:
mov r7,#0x00000500 /*the 'on delay'*/
mov r8,#0x00000050 /*the 'off delay'*/
innerLoop1$:
str r5,[r4,#40] /*turn on LED*/
add r0,r7,#0 /*cause a delay of r7 us - the on delay*/
bl Wait
str r5,[r4,#28] /*turn off LED*/
add r0,r8,#0 /*cause a delay of r8 us - the off delay*/
bl Wait
sub r7,#1
add r8,#1 /*update the duty cycle*/
cmp r8,r9 /*if the delay is above 1 second, turn off*/
/*for a second, then start over*/
bgt innerLoop2$
b innerLoop1$
innerLoop2$:
str r5,[r4,#40] /*turn on LED*/
add r0,r7,#0 /*cause a delay of r7 us - the on delay*/
bl Wait
str r5,[r4,#28] /*turn off LED*/
add r0,r8,#0 /*cause a delay of r8 us - the off delay*/
bl Wait
add r7,#1
sub r8,#1 /*update the duty cycle*/
cmp r7,r9 /*if the delay is above 1 second, turn off*/
/*for a second, then start over*/
bgt outerLoop$
b innerLoop2$
Related Questions
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.