Several researchers have suggested that adding a register-memory addressing mode

Question

Several researchers have suggested that adding a register-memory addressing mode to a load-store machine might be useful. The idea is to replace sequences of
LOAD R1, 0(R3)
ADD R2, R2, R1
by
ADD R2, 0(R3)
Assume the new instruction will cause the clock to increase by 5%. (Assume that the new instruction affects only the clock cycle and not the CPI).
For a benchmark program with 25.1% LOAD instructions on the load-store machine, what percentage of the loads must be eliminated for the machine with the new instruction to have at least the same performance?

Explanation / Answer

Assume that ‘a’ is the fraction of loads which are removed , On the load store machine loads are of 25.1 % of all the instructions, If ‘a’ number of loads are eliminated from all the instructions .251a are removed .

Consider the equation ,

CPIold×ClockCycleTimeold×ICold=CPInew×ClockCycleTimenew×ICnew ,

Here the CPI does not changes ,And the new clock cycle is 1.05 times the old cycle , and we get the new instruction count as , 1-.251a

Therefore ‘a’ can be calculated , take the value of speedup as 1 because the performance is same,

1=(1.251a)×1.05

1=1.05.26355a

.05= -.26355a

a= -0.5/.26355

a= 0.189

a=0.19

Hence 19% of the loads must be eliminated for the machine with the new instruction to have at least the same performance.

Related Questions

Navigate

• Browse (All)
• Browse S
• Subjects

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.