Consider a hypothetical 32-bit microprocessor having 32-bit instructions compose

Question

Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two fields. The first byte contains the opcode and the remainder an immediate operand or an operand address.

a.) What is the maximum directly addressable memory capacity (in bytes)?

b.) Discuss the impact on the system speed if the microprocessor bus has

1.) a 32-bit local address bus and a 16-bit local data bus, or

2.) a 16-bit local address bus and a 16-bit local data bus.

c.) How many bits are needed for the program counter and the instruction register?

Explanation / Answer

Given that,
a)
There are 32-bit microprocessors with 32-bit instruction
From left side first 8 bits are opcode
Then operand = 24 bits
So that maximum directly addressable memory capacity = 2^24
= 16777216

b)the impact on the system speed if the microprocessor bus has
1.) a 32-bit local address bus and a 16-bit local data bus:
As per given local address bus is 32-bit,and we also have 32-bit instruction,the entire address can be decoded once.
And given that data bus is 16-bits, to fetch 32-bit instrcution we need two cycles.

2)
local address bus is 16-bit,and we have 32-bit instruction, sp that to fetch the instruction it takes two cycles.
Local data bus also 16-but, again it takes two cycles.
Totally 4 cycles.

c) No.of operands = 24 bits
Since operands are 24 bits, program counter needs atlease 24 bits.
Instruction register stores present instruction, hence it needs 32-bits

Related Questions

Navigate

• Browse (All)
• Browse C
• Subjects

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.