In need help with this lab for this things: - Verilog code for ALU module and te

Question

In need help with this lab for this things:

- Verilog code for ALU module and testbench simulation waveform

- Generated schematic

In this lab, we are going to design a 8 bit ALU with reset in Verilog For input: 8-bit data signal A and B,, 3 bit signal Opcode reset signal reset. For output: 16 -bit data signal result. when reset = 1 , result = 0 And reset 0, the ALU should function according the opcode(Refer table 1) Table 1: Opcode Operation A B A-B 001 010 011 100 101 110 AIB (AIB) A & B (A & B) If reset signal is active, there reset will be all zeros. When reset is inactive your ALU should operate. Figure below shows the black box view of ALU

Explanation / Answer

case(opcode)

3'b000 : result <= {7'b0,A+B} ; // A+B gives the output of 9 bits = sum 8 bits and carry 1 bit. So concatenated with 7 bits of zeros at the begining.

3'b001 : result <= {7'b0,A-B} ; // A-B also gives 9 bit output. 8 bit difference and 1 bit borrow

3'b010 : result <= A*B ;

3'b011 : result <= {8'b0,A|B};

3'b100 : result <= {8'b0,(~A|B)};

3'b101 : result <= {8'b0,A&B};

3'b110 : result <= {8'b0,~(A&B)};

3'b111 : result <= {8'b0,A^B};

endcase

For the testbench module :

initial begin

reset = 1 ;

#10

reset = 0;

for (i=0;i<=7,i=i+1)

begin

opcode = i ;

A = 8'b11111111;

B = 8'b00000001;

#10;

end

end

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