Assume a five-stage single-pipeline microarchitecture (fetch, decode, execute, m

Question

Assume a five-stage single-pipeline microarchitecture (fetch, decode, execute, memory, write back) and the code below. All ops are 1 cycle except LW and SW, which are 1 + 2 cycles, and branches, which are 1 + 1 cycles. There is no forwarding. Show the phases of each instruction per clock cycle for one iteration of the loop.

a. How many clock cycles per loop iteration are lost to branch overhead?

b. Assume a static branch predictor, capable of recognizing a backwards branch in the Decode stage. Now how many clock cycles are wasted on branch overhead?

c. Assume a dynamic branch predictor. How many cycles are lost on a correct prediction?

Loop: LHR3,0(RO) L R1,0 (R3) ADDI R1,R1,#1 SUB R4, R3,R2 S R1,0 (R3) BNZ R4, Loop

Explanation / Answer

Solution-1a

Next loop iteration will start at clock cycle = 16

Solution-1b

Next loop iteration will start at clock cycle = 14. So, 2 cycles is wasted on branch overhead.

Solution-1c

Next loop iteration will start at clock cycle = 13. So, 1 cycle is wasted on correct prediction

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 F D E M M M W F D -- -- -- E M M M W F -- -- -- D -- -- -- E M W F -- -- -- D E M W F D E M M M W F D E E -- M W F D E M M M W

Related Questions

Navigate

• Browse (All)
• Browse A
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.