Q1 (10 points) Answer with \"True\" or \"False\". The ALU along with the registe
ID: 3901895 • Letter: Q
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Q1 (10 points) Answer with "True" or "False". The ALU along with the registers and the connecting buses form the path of a CPU A translator converts programs in one language to another. The Hamming distance between 0101010 and 1000100 is 4. If the minimum distance of a code is d, then this code can correct at most d 1 errors e_SIMD architecture consists of a single control unit and multiple processing elements. (f caches mecmiFully aspciaive caches are morlex and codty than diret mapod Increasing the degree of associativity of a set-associative cache will increase The pipelining technique achieves concurmency by replicating the hardware The hit rate can be increased by splitting a unified cache into two caches of RISC architecture has a microarchitecture layer. the miss rate. module. equal size, one for instructions and one for data. 0)Explanation / Answer
(a). TRUE. ALU along with registers(of ALU) and the connecting buses form the data path of a CPU.
(b). TRUE. A Translator is a program that is used to perform translation of a given program written in some programming language(Exampple C, FORTRAN) into a functionally equivalent program (target language or low level language)
(c). FALSE. Hamming distance between two binary numbers is number of 1's in bit-wise EX-OR operation of given binary numbers. Thus, hammming distance in this case will be 5 not 4.
(d). FALSE. Minimum distance required to correct d bit errors is 2d-1.
(e). TRUE. SIMD(Single Instruction Multiple Data) has single Control Unit and multiple Processing Unit.
(f). TRUE. Fully associative caches are more complex and expensive than direct-mapped cache due to very large number of comparators. Cost goes high and complexity to implement parallel comparators increases a lot.
(g) FALSE. Increasing associativity in set-associative cache will reduce number of conflict misses and may reduce the miss rate.
(h) TRUE. Pipelining technique achieves concurrency by replication of hardware module.
(i) FALSE. Split cache is helpful in reducing thrashing but not hit rate.
(j) TRUE. RISC architecture has a microcontroller unit and has a micro architecture.
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