Q1 (10 points) Answer with \"True\" or \"False\" The ALU along with the register

Question

Q1 (10 points) Answer with "True" or "False" The ALU along with the registers and the connecting buses form the data A translator converts programs in one language to another. path of a CPU. The Hamming distance between 0101010 and 1000100 is 4. 1 errors. elementis. Fuly associ cachesFully the miss rate. If the minimum distance of a code is d, then this code can correct at most d - SIMD architecture consists of a single control unit and multiple processing Fully associative caches are more complex and costly than direct-mapped Increasing the degree of associativity of a set-associative cache will increase The pipelining technique achieves concurrency by replicating the hardware module. 0The hit rate can be increased by splitting a unified cache into two caches of equal size, one for instructions and one for data. 0) RISC architecture has a microarchitecture layer.

Explanation / Answer

SOLUTION:

This solution having answer in true or false and explanation for each question for

clear and better understanding.

Answer for given questions:

a. true
ALu which perform the arithmetic and logical processing .
Registers which is used for storing purpose.
i.e for memory
Buses are used for transfering addresses between two devices or memory.
It is a simply wires.

and datapath are combination of all these.

b. true
yes translator converts program in one language to other without changing the logic part.
It converts the syntax to equivalent language.

c. false

hamming distance : how may corresponding positions of two string are different from each other.

for example:
        positions:
        1234567
string1=0101010
string2=1000100

positions of bits which are not same : 1,2,4,5,6

so total hamming distance =5

d.true
yes minimum distance of a code having value d then it can atmost detect d-1 errors.

e.true
SIMD : single instruction multiple data
SIMD is powerful architecture that performs actions on different data values.
it consists of many processor for processing th data .

f. true
Direct mapping having single comparator and multiplixer for entry.
whereas Fully Associative cache have multiple comparator and multiplixer that results it more complex and costly.

g. False
basically higher the degree of associativity of a set-associative cache ,lower the miss rate ,because hit time will increase so miss rate will be reduced .

h. true
because in pipelining parallel processing is done that's why pipelining techinique achieves concurrency by replicating the hardware.

i. true.
because by this way miss rate will be reduced .so hit rate will be increased .

j. true
RISC: reduced instruction set computer
RISC is mainly used for higher speed by minimising computing instruction .
That's why it having microcontroler layer.

since everyting is provided for better and clear understanding .

However further if any difficulty in understanding   then feel

free to ask .

i will help you.

Related Questions

Navigate

• Browse (All)
• Browse Q
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.