please anybody answer about it 13. [4+6]Considering the architecture diagram con
ID: 3909070 • Letter: P
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please anybody answer about it
13. [4+6]Considering the architecture diagram containing 5 stages as identified here, answer the following questions Add Ad a. What is the purpose of 2 adders? Data Register # Register # Register # PC Address Instruction Registers ALU?..! Address Instruction memory Data memory Data b. Considering we need 2 ns for stage 1, 3 for stage 2, 5 for stage 3, 5 for stage 4 and 6 ns for stage 6 respectively, Considering a single cycle approach what will be duration of the cycle to complete unconditional jump instruction? i. Considering a multi-cycle approach how many cycles will it take to complete add instruction? ii.Explanation / Answer
a) First adder is used to increament Program Counter(PC) register Because every time Instruction is loaded into pipeline address of next instruction must be in PC.
Second adder is add step size to current PC value in case of PC relative addressing mode.
b)
i) For single cycle longest stage delay is our cycle time.So cycle time here is 6ns for all stages.
ii) 6 cycle for multicycle add instruction.
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