Squidward has decided to branch out into hardware design. Being new to the field

Question

Squidward has decided to branch out into hardware design. Being new to the field, he's asking for your help in designing a pipeline of a new processor. Once the processor has been built, he's going to test it with a sample program that contains 2x109 instructions (a). If the new processor were a non-pipelined, single cycle design and each instruction took 860 ps to finish, how long would it take to execute the sample program? (b). If the new processor were a non-pipleined multi cycle design with the longest stage taking 140 ps to finish, how long would it take to execute the sample program? (You may assume instructions average out at 4 cycles each) (c). Assume the current state-of-the-art pipeline has 15 stages. Assume also that the stages are y balanced. How much speedup will it achieve compared to the non-pipelined single cycle processor? Be exact here! (d). Realistically, we cannot achieve ideal speedup due to the overhead of implementing pipelining stages (e.g. imperfectly balanced stages, adding pipeline registers, etc). Does this overhead affect the instruction latency, instruction throughput, or both? For each metric affected, is the effect significant? Why or why not?

Explanation / Answer

a).cycle=1

    time=860 ps

     Single Cycle Machine • 860 ps/cycle x 1 CPI x 2*10^9 inst = 1.72 sec

b).

   140 ps/cycle x 4 CPI (avg) x 2*10^9 inst = 1.12 sec

c).

   stages=15

ideal speed up for pipeline= number of stages =15

d)

    Pipelining reduces the cycle time to the length of the longest stage plus the register delay. Latency becomes CT*N where N is the number of stages as one instruction will need to go through each of the stages and each stage takes one cycle. The throughput formula remains the same.
Pipeline Latency = n Gate Delay + (p-1) register delays

    p: no of stages

Improves throughput at the expense of latency

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