a)Determine the number of clock cycles needed to execute this code segment on th

Question

a)Determine the number of clock cycles needed to execute this code segment on the
pipelined implementation of the MIPS processor (5-stage pipeline).

b) Identify the registers that are read during clock cycle #4. (Explain how you got the answer)

c) Identify the register that is written during clock cycle #6. (Explain how you got the answer)

3. [5] Pipeline Operation (5-stage MIPS pipeline). Consider the MIPS assembly language code segment given below. I1: add $s0, ?s1, $S2 I2: add $s3, $s4, $S5 I3 add $s6, $s7, $zero I4: add $t0, $tl, $t2 I5: add $t3, $t4, $t5 I6: add $t6, $t7, $t8 17: add $fp, $Sp, $zero

Explanation / Answer

a. The first instruction will take 5 clock cylces to execute in this 5-state pipeline MIPS processor. The second instruction will take one more additional cycle to complete its execution. Likewise the next instruction will take additional one cycle to its previous instruction. Thus in total to execute all seven instruction it takes:

5+1+1+1+1+1+1=11 clock cycles. In the table below, each instruction with its 5 stages along the time(clock cycle) is given:

b. The registers are read in the ID(Instruction Decode) stage in this 5-stage pipeline implementation. Therefore in clock cyle 4, Instruction 3 is in ID stage in the execution of the given code segment. The instruction I3:

add $s6,$s7,$zero

is in ID stage, the two operands that are read are $s7 and $zero. $zero is an immediate value and $s7 is a register. Hence only one register is read. Therefore the register that is read during clock cycle #4 is $s7

c. The registers are written in WB(Write Back) stage in the 5-state pipeline. In clock cycle #6, Instruction 2 is in WB stage of 5-stage pipeline. Instruction 2:

add $s3,$s4,$s5

The destination register is $s3 which is assigned a summation of values in registers $s4 and $s5. Hence the result is written in the destination register $s3 in Write Back stage in clock cycle #6.

Inst/Clk Cycle: 1 2 3 4 5 6 7 8 9 10 11 Inst 1 IF ID EXE M WB Inst 2 IF ID EXE M WB Inst 3 IF ID EXE M WB Inst 4 IF ID EXE M WB Inst 5 IF ID EXE M WB Inst 6 IF ID EXE M WB Inst 7 IF ID EXE M WB

Related Questions

Navigate

• Browse (All)
• Browse A
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.