N. Write a Verilog code that describes the following figure. The figure represen
ID: 3920700 • Letter: N
Question
N. Write a Verilog code that describes the following figure. The figure represents the register file (32x32) with its inputs and outputs as shown. Assume that the register outputs are updated asynchronously but writing to the register is updated with an available address at wn (not-0),we signal-1, synchronously with every positive edge clock cycle and synchronously with the (rst signal-1). You have to reset all the register values when there is a reset signal. (4 points) 5-bit register number of read portA regtile 32-bitdata of read portA 32-bit data of read port B 5-bit register number ofread patB-- q431 maloj wn(4 ' 5-bit register number of write port ?- 32-bit data of write portd310 write enableWe cirn dock dearExplanation / Answer
/* module definition for the module */
module register_file(input [4:0] ma,
input [4:0] mb,
input [4:0] wn,
input [31:0] d,
input we, clock, clear,
output reg [31:0] qa,qb);
reg [31:0] regfile [31:0];
always@(posedge clock or posedge clear)
begin
if(clear) begin
/* clearing the contents of regfle*/
regfile[0] <= 32'd0;
regfile[1] <= 32'd0;
regfile[2] <= 32'd0;
regfile[3] <= 32'd0;
regfile[5] <= 32'd0;
regfile[6] <= 32'd0;
regfile[7] <= 32'd0;
regfile[8] <= 32'd0;
regfile[9] <= 32'd0;
regfile[10] <= 32'd0;
regfile[11] <= 32'd0;
regfile[12] <= 32'd0;
regfile[13] <= 32'd0;
regfile[14] <= 32'd0;
regfile[15] <= 32'd0;
regfile[16] <= 32'd0;
regfile[17] <= 32'd0;
regfile[18] <= 32'd0;
regfile[19] <= 32'd0;
regfile[20] <= 32'd0;
regfile[21] <= 32'd0;
regfile[22] <= 32'd0;
regfile[23] <= 32'd0;
regfile[24] <= 32'd0;
regfile[25] <= 32'd0;
regfile[26] <= 32'd0;
regfile[27] <= 32'd0;
regfile[28] <= 32'd0;
regfile[29] <= 32'd0;
regfile[30] <= 32'd0;
regfile[31] <= 32'd0;
end
else if(we) begin
/* writing the data to regfile
* if write enable */
regfile[wn] <= d;
end
/* output port is updated with
* the values in the regfile */
qa <= regfile[ma];
qb <= regfile[mb];
end
endmodule
/* hope this helps, if any queries please do comment */
/* thanks */
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