N. Write a Verilog code that describes the following figure. The figure represen

Question

N. Write a Verilog code that describes the following figure. The figure represents the register file (32x32) with its inputs and outputs as shown. Assume that the register outputs are updated asynchronously but writing to the register is updated with an available address at wn (not -0), we signal -1, synchronously with every positive edge clock cycle and synchronously with the (rst signal-1). You have to reset all the register values when there is a reset si gnal. (4 points) 5-bit register number of read port A regtile 32-bit data of read portA 5-bit register number ofread portB* 5-bit register number of write port b4o 132-bit data of read portB 32-bit data of write port> d31:0] we write enable clock clear clrn

Explanation / Answer

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity regfile is

Port ( Ma : in std_logic_vector(4 downto 0);

Mb : in std_logic_vector(4 downto 0);

Wn : in std_logic_vector(4 downto 0);

clrn : in std_logic;

clk : in std_logic;

busD:in std_logic_vector(31 downto 0);

busA : out std_logic_vector(31 downto 0);

busB : out std_logic_vector(31 downto 0));

end regfile;

architecture Behavioral of regfile is

type reg_file is array (31 downto 0) of std_logic_vector(31 downto 0);

signal regarray:reg_file(0 to 31):=(x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000");

begin

process(Ma,Mb,Wn,Clrn,clk,busD)

variable addr_a,addr_b,addr_w:integer;

begin

addr_a:=CONV_INTEGER(Ma);

addr_b:=CONV_INTEGER(Mb);

addr_w:=CONV_INTEGER(Wn);

busA<=regarray(addr_a);--Read R[Ma]

busB<=regarray(addr_b);--Read R[Mb]

if (clk'event and clk='1') then ----wait for active clock edge

if (Clrn='1') then --—see if write signal is active

regarray(addr_d)<=busD;--write the data

end if;

end if;

end process;

end Behavioral;

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