N. Write a Verilog code that describes the following figure. The figure represen
ID: 1372608 • Letter: N
Question
N. Write a Verilog code that describes the following figure. The figure represents the register file (32x32) with its inputs and outputs as shown. Assume that the register outputs are updated asynchronously but writing to the register is updated with an available address at wn (not 0), we signal 1, synchronously with every positive edge clock cycle and synchronously with the (rst signal-1). You have to reset all the register values when there is a reset signal. (4 points) 5-bit register number ofread port A 5-bit register number of read portB 5-bitregister number of write port 32-bit data of write port write enable clock clear regtile mal40) #310132-bit data of read port A 0 b31032-bit data of read port B wn/4.0 d131 clrnExplanation / Answer
module reg_file(qa,qb,we,wn,clk,clr,ma,mb,data);
output reg [31:0]qa,qb;
input clk,clr,we;
input [4:0]wn;
input [4:0]ma,mb;
input [31:0]data;
reg [31:0] regfile[0:31];
integer i;
always @(posedge clk) //synchronous write and reset
if (clr)
begin
for(i=0; i<32; i=i+1)
regfile[i]<=32'd0;
end
else
begin
if(we)
regfile[wn]<=data;
end
always @(*) //asynchronous output
begin
qa<=regfile[ma];
qb<=regfile[mb];
end
endmodule
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