If a set of waveforms are applied to SR and D flip-flops as shown in the figure,

Question

If a set of waveforms are applied to SR and D flip-flops as shown in the figure, and these waveforms are applied to the flip-flops shown along with the values of their timing parameters, which one(s) of the following statements are true?

More than one answer may be correct. Please explain how you arrived at your answer(s).

(a) For flip-flop with inputs S1 and R1, there is a setup time violation at 24 ns and an input combination violation around 28 ns.

(b) For flip-flop with input D2, there is a setup time violation at 28 ns.

(c) For flip-flop with inputs S1 and R1, there is a hold time violation before 24 ns.

(d) For flip-flop with input D3, there is a hold time violation at 16 ns and a setup time violation at 24 ns.

(e) For flip-flop with inputs S1 and R1, there is a setup time violation just before 24 ns.

If a set of waveforms are applied to SR and D flip-flops as shown in the figure, and these waveforms are applied to the flip-flops shown along with the values of their timing parameters, which one(s) of the following statements are true? More than one answer may be correct. Please explain how you arrived at your answer(s). (a) For flip-flop with inputs S1 and R1, there is a setup time violation at 24 ns and an input combination violation around 28 ns. (b) For flip-flop with input D2, there is a setup time violation at 28 ns. (c) For flip-flop with inputs S1 and R1, there is a hold time violation before 24 ns. (d) For flip-flop with input D3, there is a hold time violation at 16 ns and a setup time violation at 24 ns. (e) For flip-flop with inputs S1 and R1, there is a setup time violation just before 24 ns.

Explanation / Answer

Set up time is the time that the inputs to a flip flop should be stable before the active clock edge. If it is not so then set up violation occurs.

hold time is the time that the inputs should be stable after the active clk edge. if it is not so then hold violation occurs.

Now coming to the question and its options..

lets go one by one....

----->>>SR flip flop is a negative edge triggered flip flop.

at 24ns,S1 is stable but R1 just makes the transition from 0 to 1.. it should have been stable atleast ts = 4ns before this... So there is a set up violation

but there is no wrong input combination at 28 ns....S1=1 and R1=0

----->>>>at 28 ns D2 makes a transition from 0 to 1 and also the clk rises. it is positive edge triggerd flop

   D2 should have been stable atleast ts i.e 1ns before the clk rising edge... so there is a set up violation.

So    b

------->>>>hold time of SR is 0ns so no hold violation

------>>>>D3 is negative triggered flop and at 16 ns clk (1 to 0 occurs) and also D3 comes down to 0. It should be stable for atleast th = 0.5 ns... so it is a hold violation

and also at 24 ns clk (1 to 0) and D3 (0 to 1) occurs at same time.. the input D3 should be stable ts = 1 ns before this.. so set up violation

SO d

---->>> e it is already explained in the option 1

So the answers are    b,d ,e

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