Q1. Consider a system with two CPU\'s. Suppose they share a single control stack
ID: 645068 • Letter: Q
Question
Q1. Consider a system with two CPU's. Suppose they share a single control stack-- the stack where old PC, PSW values are stored when an interrupt occurs. What could go wrong with this scheme? Explain in LESS THAN 50 WORDS. Q2. Assume the following: (a) The interrupt vector is properly loaded. (b) Somehow, all the service routines have been wiped out they have al]. become all zeroes. (C) The leftmost bit of the Op Code of any valid instruction is 1. Now suppose a user executes a system call. What will happen? Explain in LESS THAN 50 WORDS. Q3. Consider the following code. What are all the possibilities regarding the output from this program? Give a scenario for each such possibility. Q4. Consider the following code. at is the MINIMUM value printed? at is the MAXIMUM value printed?Explanation / Answer
Q1.
When a processor responds to an interrupt, certain sensitive phases of the interrupt processing are protected from interruption by another interrupt. In general, though, the execution of the bulk of an interrupt handler is itself interruptible, meaning that the execution of the handler can be suspended in order to take another interrupt, whose handler has to run to completion (return) before the original handler can be restarted: the interrupts nest.
Usually there is a priority scheme in place: certain interrupts can interrupt the handlers of certain other interrupts, whereas others are blocked. (Historically, there have been many schemes: from fixed numeric priorities, to completely flexible masks.) Usually it makes sense to block the same interrupt while its own handler is executing; but that doesn't work in some situations (such as a signal being shared among multiple devices).
When two interrupt requests are raised at the same time, and both are unmasked, a given processor can only respond to one of them. Historically, this is dealt with by some piece of hardware (perhaps called an "interrupt controller") which multiplexes the interrupt lines and makes a decision about which interrupt gets through, based on some priority scheme (perhaps programmable, or else fixed). Two interrupts cannot be serviced at the same time: at least some key portion of the actions of servicing an interrupt is necessarily serialized: the portion when the CPU acknowledges the interrupt and dispatches a handler. At some point, the CPU can be made ready to handle the other interrupt which has remained pending.
Q2.
A driver of a physical device that receives interrupts registers one or more interrupt service routines (ISR) to service the interrupts. The system calls the ISR each time it receives that interrupt.
Devices for ports and buses prior to PCI 2.2 generate line-based interrupts. A device generates the interrupt by sending an electrical signal on a dedicated pin known as an interrupt line. Versions of Microsoft Windows prior to Windows Vista only support line-based interrupts.
Beginning with PCI 2.2, PCI devices can generate message-signaled interrupts. A device generates a message-signaled interrupt by writing a data value to a particular address. Windows Vista and later operating systems support both line-based and message-signaled interrupts.
The system supports two different types of ISRs:
The driver can register an InterruptService routine to handle line-based or message-signaled interrupts. (This is the only type available prior to Windows Vista.) The system passes a driver-supplied context value.
The driver can register an InterruptMessageService routine to handle message-signaled interrupts. The system passes both a driver-supplied context value and the message ID of the interrupt message
The above scenario would almost lead to a system crash.
3.
The two Threads cooperate in multithreaded programs
? To share resources, access shared data structures
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