Assume an invalidation protocol works on a snooping bus for a single cache block
ID: 655738 • Letter: A
Question
Assume an invalidation protocol works on a snooping bus for a single cache block (X) with write-back caches. Given the sequence of CPU activities, fill in the rest of the following table.
CPU Activity
Bus Activity
CPU As Cache
CPU Bs Cache
Memory
0
CPU A reads X
CPU B reads X
CPU A reads X
CPU B writes a 1 to X
CPU A reads X
CPU B reads X
CPU A writes a 0 to X
CPU A reads X
CPU B reads X
CPU A reads X
CPU Activity
Bus Activity
CPU As Cache
CPU Bs Cache
Memory
0
CPU A reads X
CPU B reads X
CPU A reads X
CPU B writes a 1 to X
CPU A reads X
CPU B reads X
CPU A writes a 0 to X
CPU A reads X
CPU B reads X
CPU A reads X
Explanation / Answer
Answer:
CPU Activity
Bus Activity
CPU A’s Cache
CPU B’s Cache
Memory
0
CPU A reads X
Cache miss for X
0
0
CPU B reads X
Cache miss for X
0
0
CPU A reads X
Cache miss for X
0
0
CPU B writes a 1 to X
Invalidation for X
1
0
CPU A reads X
Cache miss for X
1
1
1
CPU B reads X
Cache miss for X
1
1
1
CPU A writes a 0 to X
Invalidation for X
0
1
0
CPU A reads X
Cache miss for X
0
1
0
CPU B reads X
Cache miss for X
1
1
0
CPU A reads X
Cache miss for X
0
1
0
CPU Activity
Bus Activity
CPU A’s Cache
CPU B’s Cache
Memory
0
CPU A reads X
Cache miss for X
0
0
CPU B reads X
Cache miss for X
0
0
CPU A reads X
Cache miss for X
0
0
CPU B writes a 1 to X
Invalidation for X
1
0
CPU A reads X
Cache miss for X
1
1
1
CPU B reads X
Cache miss for X
1
1
1
CPU A writes a 0 to X
Invalidation for X
0
1
0
CPU A reads X
Cache miss for X
0
1
0
CPU B reads X
Cache miss for X
1
1
0
CPU A reads X
Cache miss for X
0
1
0
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