COMPUTER ARCHITECTURE 1. For each part of this exercise, assume the initial cach
ID: 664781 • Letter: C
Question
COMPUTER ARCHITECTURE
1. For each part of this exercise, assume the initial cache and memory state in Figure 5.38. Each part of this exercise specifies a sequence of one or more CPU operations of the form:
P#: <op> <address> [ <----<value>]
where P# designates the CPU (e.g., P0,0), is the CPU operation (e.g., read or write),<address>
denotes the memory address, and indicates the new word to be assigned on a write operation. What is the final state (i.e., coherence state, sharers/owners, tags, and data) of the caches and memory after the given sequence of CPU operations has completed? Also, what value is returned by each read operation?
c. P0,0: write 128 <-- 78
PO P1 PO P1 P2 P3 P2 L25 MO M1 Figure 5.37 Multichip, multicore multiprocessor with DSM. P0,1 P3,1 25,0 25,1 DS PODE 108 00 0B 118 00 M1 Figure 5.38 Cache and memory states in the multichip, multicore multiprocessor.Explanation / Answer
A P0,0: read 100
CPU read M
P0,B0 : ( M,100,00,10)
B. P0,0: read 128
CPU read - a read miss M -> S
P0,B1 : (S,108,00,08)
C. P0,0: write 128 <-- 78
CPU write S -> M
P0,B1 : (S,108,00,78)
D. P0,0: read 120
CPU read : a read miss M->S
P0,B0 : (S,120,00,20)
e. P0,0: read 120
P0,0: a read miss M->S
P0,B0 : (S,120,00,20)
f. P1,0: read 120
CPU read S
P1,B0 : ( (S,120,00,20))
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