This is all in Verilog. i prefer we use gates and muxes etc etc, not If statment

Question

This is all in Verilog.

i prefer we use gates and muxes etc etc, not If statments

Make sure to show testing (testbench, waveform results) for each part of the project.

Design an expandable 1 bit bin/gray converter that handles the following functions:

? Binary to Gray Code Conversion

? Gray Code to Binary Conversion.

The block diagram for the 1-bit converter is as follows. The input GRAY is set to logic high when the

input to CONVIN is gray code and should be converted to binary. The input GRAY is set to logic low when

the input to CONVIN is binary and should be converted to gray code.

The 1-bit converter will be able to be expanded to a bin/gray converter of any size as shown below. In

the case below we have a 2-bit bin/gray converter.

Create a testbench to exhaustively test your expandable 1-bit bin/gray converter. The 1-bit converter

will have the following module definition:

module OneBitGrayConverter (CONVOUT, NEXTOUT, CONVIN, PREVIN, GRAY);

input CONVIN;

input GRAY;

input PREVIN;

output CONVOUT;

output NEXTOUT;

Once your converter is working, implement a 4-bit bin/gray converter using 4 instances of your 1-bit

converter module. Create another testbench to test the 4-bit converter. The 4-bit converter will have

the following module definition:

module FourBitGrayConverter(CONVOUT, CONVIN, GRAY);

input GRAY;

input [3:0]CONVIN;

output [3:0]CONVOUT;

Your Verilog must be compiled and simulated. Save a screenshot of all of the timing diagrams

(waveforms) for both the 1-bit and 4-bit versions and include these in your report.

Explanation / Answer

working code:

module bin2gray(
input sel,
input[3:0] data_in,
output[3:0] data_out
)

always @ (posedge clk)
begin
if (sel == 1'b1)
begin
data_out[3] <=data[3];
data_out[2] <=data[3] ^ data [2];
data_out[1] <=data[2] ^ data [1];
data_out[0] <=data[1] ^ data [0];
end
else
begin
data_out[3] <= data[3];
data_out[2] <= data[2] ^ data_out[3];
data_out[1] <= data[1] ^ data_out[2];
data_out[0] <= data[0] ^ data_out[1];
end
end//always block

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