I need a help for writing a VHDL code please as soon as you can In this experime

Question

I need a help for writing a VHDL code please as soon as you can In this experiment you are to implement a special counter on a CPLD. your counter will count up to 30, either in increments of 3 or 5, to be selected by a properly wired switch, here referred to as "select". You will display your count on two 7-segment display, which you will drive directly from the CPLD (you may not use 7447 drivers). You must build a 555-astable circuit as your clock, with a frequency of about I Hz. Remember to make your signal TTL compliant by running'it through two consecutive inverters. Include a propqrly wired pish-button start switch, programmed so that unless pressed the circuit will remain in an initial state in which zero is displayed on both 7-segments. The start switch will have no effect, once it has been pressed and counting has commenced. The counters will count continuously (beginning with either 0,3, 6,etc., or 0, 5, 10, etc.), wrapping appropriately back to 0, when the count reach 30. E.g. ....24, 27,30,0,3...; or ...20,25,30,0, 5, 10,.... Program so that if "select"=0, the count increments by 3, and if "select" = 1, the count increments by 5. Any change made to the value of select(0 ?1 or 1? 0) should take effect when the counter wraps. You must use VHDL, not schematiccapture, for this lab. Counters involve addition and so you must be careful how you define your vectors (if you use them). You will recall that you have two options. 1. Specify signed or unsigned and use standard logic vectors, as shown below. library IEEE; use IEEE . std_logi c_1164. all; use rEEE.std logic_unsigned.aI1; --t/eed this for addition. entity cbtest is port ( Clock: i_n std logic; Sum: buffer std_Iogic_vector (3 downto 0) ) ,. --std fogic_vectors must be used with unsigned. end'cbtest; 2. Invoke "std logic-arith.all" and use signed or unsigned for your vectors. library IEEE,.

Explanation / Answer

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity debounce is Port ( clock : in std_logic; keyin : in STD_LOGIC_VECTOR (3 downto 0); keyout : out STD_LOGIC_VECTOR (3 downto 0)); end debounce; architecture behaviour of debounce is signal clk: std_logic; begin milli_s_period: process(clock) variable cnt: std_logic_vector (30 downto 0); begin if rising_edge(clock) then cnt := cnt + '1'; --if cnt = "000000000000011" then -- test if cnt = "110001001010111" then cnt := "000000000000000"; clk

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