VHDL programming Q5 State with justification what the following code segment com
ID: 2072559 • Letter: V
Question
VHDL programming
Q5 State with justification what the following code segment comprising 3 sequential
assertions will report for each of the following cases:
(i) A=’0’, B=’0’
(ii) A=’0’, B=’1’
(iii) A=’1’, B=’0’
(iv) A=’1’, B= ‘1’
assert(not A or B)
report “ Case 1”
severity note;
assert (A xor B)
report “Case 2”
severity note;
assert (not(not A and B))
report “Case 3”
severity note;
Explanation / Answer
ANSWER:
Any assertion gets fired if the condition based on which the assertion is written comes to 1.
1. In this case, Not A = 1 and Not B =1. So, looking at all the assertions, only Case 3 gets fired since no(not A and B) equals 1.
2. In this case, Not A = 1 and Not B =0. So, looking at all the assertions, only Case 2 gets fired since A xor B equals 1.
3. In this case, Not A = 0 and Not B =1.. So, looking at all the assertions, Case 1 and Case 2 both get fired since A xor B and (not A or B) both equal 1.
4. In this case, Not A = 0 and Not B =0. So, looking at all the assertions, Case 1 and Case 3 get fired since not(not A and B) and (not A or B) both equal 1.
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