VHDL test bench problem. I have to make an 8 bit ALU and I am confused because I
ID: 2989804 • Letter: V
Question
VHDL test bench problem. I have to make an 8 bit ALU and I am confused because I get error when I run this code. I get errors near the bottom when I designate the test cases.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ALU_TB IS
END ALU_TB;
ARCHITECTURE behavior OF ALU_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Arithmetic
PORT(
a : IN std_logic_vector(7 downto 0);
b : IN std_logic_vector(7 downto 0);
CTRL : IN std_logic_vector(2 downto 0);
zero : OUT std_logic;
overflow : OUT std_logic;
y : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(7 downto 0) ;
signal b : std_logic_vector(7 downto 0) ;
signal CTRL : std_logic_vector := "000";
--Outputs
signal y : std_logic_vector(7 downto 0);
signal zero : std_logic;
signal overflow : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Arithmetic PORT MAP (
A => A,
B => B,
CTRL => CTRL,
Y => Y,
overflow => overflow,
zero => zero
);
-- Stimulus process
-- insert stimulus here
CTRL <= "000"; -- pass A
a <= a"F"; b <= b"F"; wait for 20 ns;
a <= a"7"; b <= b"2"; wait for 20 ns;
a <= a"8"; b <= b"3"; wait for 20 ns;
a <= a"A"; b <= b"C"; wait for 20 ns;
a <= a"B"; b <= b"4"; wait for 20 ns;
a <= a"0"; b <= b"0"; wait for 20 ns;
CTRL <= "001"; -- A + B
a <= a"F"; b <= b"F"; wait for 20 ns;
a <= a"7"; b <= b"2"; wait for 20 ns;
a <= a"8"; b <= b"3"; wait for 20 ns;
a <= a"A"; b <= b"C"; wait for 20 ns;
a <= a"B"; b <= b"4"; wait for 20 ns;
a <= a"0"; b <= b"0"; wait for 20 ns;
CTRL <= "010"; -- A - B
a <= a"F"; b <= b"F"; wait for 20 ns;
a <= a"7"; b <= b"2"; wait for 20 ns;
a <= a"8"; b <= b"3"; wait for 20 ns;
a <= a"A"; b <= b"C"; wait for 20 ns;
a <= a"B"; b <= b"4"; wait for 20 ns;
a <= a"0"; b <= b"0"; wait for 20 ns;
CTRL <= "011"; -- Not A + 1
a <= a"F"; b <= b"F"; wait for 20 ns;
a <= a"7"; b <= b"2"; wait for 20 ns;
a <= a"8"; b <= b"3"; wait for 20 ns;
a <= a"A"; b <= b"C"; wait for 20 ns;
a <= a"B"; b <= b"4"; wait for 20 ns;
a <= a"0"; b <= b"0"; wait for 20 ns;
CTRL <= "100"; -- Not A
a <= a"F"; b <= b"F"; wait for 20 ns;
a <= a"7"; b <= b"2"; wait for 20 ns;
a <= a"8"; b <= b"3"; wait for 20 ns;
a <= a"A"; b <= b"C"; wait for 20 ns;
a <= a"B"; b <= b"4"; wait for 20 ns;
a <= a"0"; b <= b"0"; wait for 20 ns;
CTRL <= "101"; -- A and B
a <= a"F"; b <= b"F"; wait for 20 ns;
a <= a"7"; b <= b"2"; wait for 20 ns;
a <= a"8"; b <= b"3"; wait for 20 ns;
a <= a"A"; b <= b"C"; wait for 20 ns;
a <= a"B"; b <= b"4"; wait for 20 ns;
a <= a"0"; b <= b"0"; wait for 20 ns;
CTRL <= "110"; -- A or B
a <= a"F"; b <= b"F"; wait for 20 ns;
a <= a"7"; b <= b"2"; wait for 20 ns;
a <= a"8"; b <= b"3"; wait for 20 ns;
a <= a"A"; b <= b"C"; wait for 20 ns;
a <= a"B"; b <= b"4"; wait for 20 ns;
a <= a"0"; b <= b"0"; wait for 20 ns;
CTRL <= "111"; -- A xor B
a <= a"F"; b <= b"F"; wait for 20 ns;
a <= a"7"; b <= b"2"; wait for 20 ns;
a <= a"8"; b <= b"3"; wait for 20 ns;
a <= a"A"; b <= b"C"; wait for 20 ns;
a <= a"B"; b <= b"4"; wait for 20 ns;
a <= a"0"; b <= b"0"; wait for 20 ns;
wait;
end process;
END;
Explanation / Answer
in ur test bench change all hexa decimal values into binary value and apply because the std_logic_vector didnt accept hexa decimal values.. i f u want give the full requirement of this problem i can give better coding for this problem
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