1) In Lab #7 Latches Flip-Flops and Counters\" you were given module JK FlipFlop

Question

1) In Lab #7 Latches Flip-Flops and Counters" you were given module JK FlipFlop and its characteristic table Write test bench module JK FlipFlop tb that verifies module JK FlipFlop performance Your vvp output should look like what follows without the "Notes" column GTKWave results are not required, but might help your development. Tips $display; outputs a blank line It is possible to define an entire row of the table in a single line of Verilog You might find it easier to understand your code if your delays are put at the end of a line, for example #1 comment", instead of at the beginning of the following line Be sure your code follows all of our Verilog Standards nPr nclr Clk J K Q Qn Notes x 0 X X X 0 1 Clear 1 X X X 1 0 Preset. Clear X X X 0 1 0 0 1 1 1 0 1 0 Set Preset. X X X 0 0 1 1 0 1 0 1 0 Reset Clear X X X 0 1 1 0 1 1 1 1 1 1 0 Toggle

Explanation / Answer

module JK_FlipFlop_tb;

reg nPr, nClr, Clk, J, K;

wire Q, Qn;

JK_FlipFlop jk1 (nPr, nClr, Clk, J, K, Q, Qn);

initial

begin

$display("nPr nClr Ck J K Q Qn");

$display("===================");

$monitor("%b %b %b %b %b b %b", nPr, nClr, Clk, J, K, Q, QNn);

nClr = 0; #10;

nPr = 1; nClr = 0; #10;

nClr = 0; nPr = x; #10;

nClr = 1; nPr = 1; Clk = 0; J = 1; K = 0; #10;

Clk = 1;

Clk = x; nClr = x; nPr = 0; J = x; K = x; #10;

nClr = 1; nPr = 1; Clk = 0; J = 0; K = 1; #10;

Clk = 1;

Clk = x; nClr = 0; nPr = x; J = x; K = x; #10;

nClr = 1; nPr = 1; Clk = 0; J = 1; K = 1; #10;

Clk = 1;

Clk = x; nClr = 1; nPr = 0; J = x; K = x; #10;

nClr = 1; nPr = 1; Clk = 0; J = 1; K = 1; #10;

Clk = 1;

   nClr = 1; nPr = 0; Clk = x; J = x; K = x; #10;

nClr = 1; nPr = 1; Clk = 0; J = 1; K = 1; #10;

Clk = 1;

nClr = 0; nPr = 1; Clk = x; J = x; K = x; #10;

nClr = 1; nPr = 1; Clk = 0; J = 0; K = 0; #10;

Clk = 1;

nClr = 1; nPr = 0; Clk = x; J = x; K = x; #10;

nClr = 1; nPr = 1; Clk = 0; J = 0; K = 0; #10;

Clk = 1;

endmodule

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