In VHDL language we can describe a variable-size counter by using a generic decl
ID: 2081165 • Letter: I
Question
In VHDL language we can describe a variable-size counter by using a generic declaration. An example of an n-bit counter is shown as follows library feee: use ieee.std_logic_1164.all: use ieee.std_logic_arith.al1: use ieee.std_logic_signed.al1: entity counter is generic (n:- natural 4;); port (clock: in STD_LOGIC: reset_n: 1n STD_LOGIC; 0: out STO_LOGIC_VECTOR(n-1 downto 0)): end entity: architecture rtl of counter is signal value: std_logic_vector(n-1 downto 0): begin PROCESS(clock. reset_n) begin if (reset_n - '0') then value '0'): elsif ((clock'event) and (clock - '1')) then valueExplanation / Answer
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all ;
ENTITY count8 IS
generic ( n : natural :=8; -- 8bit length of counter
k : natural :=256);
PORT ( Key0_reset : IN STD_LOGIC ; -- An asynchronous Reset(assuming active low type)
key1_clk : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR ( n-1 DOWNTO 0) ) ;
END count8 ;
ARCHITECTURE Behavior OF count8 IS
SIGNAL Count : STD_LOGIC_VECTOR (n-1 DOWNTO 0) ;
BEGIN
PROCESS ( key1_clk, Key0_reset )
BEGIN
IF (Key0_reset = '0') THEN
Count <= (OTHERS => '0');
ELSIF (key1_clk'EVENT) AND (key1_clk ='1') THEN
IF( Count = k-1) THEN
Count <= (OTHERS => '0');
ELSE
Count <= Count + 1 ;
END IF;
END IF ;
END PROCESS ;
Q <= Count ;
END Behavior ;
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