Complete Problem 1. Simulate all input combinations for this SOP (Sum-of-Product

Question

Complete Problem 1. Simulate all input combinations for this SOP (Sum-of-Products) expression. However, be aware that specific input sequences are required to observe a timing hazard. The problem states that you will need to observe the output when B and C are both high (logic 1) and A transitions from high to low to high (logic 1 to 0, then back to 1).

Problem 1.     Implement the function Y = A’.B + A.C in the VHDL tool. Define the INV, OR and two AND operations separately, and give each operation a 1ns delay. Simulate the circuit with all possible combinations of inputs. Watch all circuit nets (inputs, outputs, and intermediate nets) during the simulation. Answer the questions below.

Observe the outputs of the AND gates and the overall circuit output when B and C are both high, and A transitions from H to L and then from L to H (you may want to create another simulation to focus on this behavior). What output behavior do you notice when A transitions?

What happens when A transitions and B or C are held a ‘0’?

Explanation / Answer

library ieee;

use ieee.std_logic_1164.all ;

entity function1 is

port ( A : in std_ulogic;

B : in std_ulogic ;

C : in std_ulogic ;

Y :out std_ulogic);

end function1;

architecture decription of function1 is begin

P1: process

variable temp1: bit ;

variable temp2: bit ;

variable temp3: bit ;

begin
temp1 <= not A after 1 ns;

temp2 <= A AND C after 1ns;

temp3 <= temp1 AND B after 1ns;

Y <= temp2 OR temp3 after 1ns;

end description

When B=C=1, and A transitions from H to L and then from L to H ;

Y reduces to "Abar OR A";

o/p Y will be falling to L following A but before it reaches 'L' voltage again it rises back to H. During this duration, o/p Y goes to 'X'. Overall Y looks like H->X->H

When B=C=0, and A transitions from H to L and then from L to H ; o/p Y stays at 0.

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