Can someone help me with the following question \"Caches are important to provid
ID: 2246916 • Letter: C
Question
Can someone help me with the following question
"Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses.
3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253
5.2.2 [10] <COD §5.3> For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty."
I have the solutions done already as you can see below
Memory
Binary
Tag
Index
Offset LSB
Hit / Miss
3
00000011
0000
011
1
miss
180
10110100
1011
010
0
miss
43
00101011
0010
101
1
miss
2
00000010
0000
001
0
hit
191
10111111
1011
111
1
miss
88
01011000
0101
100
0
miss
190
10111110
1011
111
0
hit
14
00001110
0000
111
0
miss
181
10110101
1011
010
1
hit
44
00101100
0010
110
0
miss
186
10111010
1011
101
0
miss
253
11111101
1111
110
1
miss
I understand how to get the binary, tag and index, however im confused on the concept of "offset lsb" and "hit / miss" can someone please explain the process of finding offeset as well as how to determine wether a number is a hit or a miss, and explain how they got the solutions for those two colums please. just trying to understand
please help
Memory
Binary
Tag
Index
Offset LSB
Hit / Miss
3
00000011
0000
011
1
miss
180
10110100
1011
010
0
miss
43
00101011
0010
101
1
miss
2
00000010
0000
001
0
hit
191
10111111
1011
111
1
miss
88
01011000
0101
100
0
miss
190
10111110
1011
111
0
hit
14
00001110
0000
111
0
miss
181
10110101
1011
010
1
hit
44
00101100
0010
110
0
miss
186
10111010
1011
101
0
miss
253
11111101
1111
110
1
miss
Explanation / Answer
Offset: Since each line consist of 2 words, last 1 digit (log22 = 1) is the offset. You can see that for all cases LSB is the offset since we have 2 words per line. (if we had 4words per line, 2bits (log24) from right or 2 bit LSB would have been the offset)
As you can see, it consist of 16 lines and each line is associated with a line number. The index from your table is matched with the line number and the tag and data bits are inserted (we are not bothered about the data field in the cache). As you start filling the table we encounter a hit if and only if tag field matches while inserting data in a particular line.
For example look at these two data sets entry:
191
10111111
1011
111
1
miss
88
01011000
0101
100
0
miss
190
10111110
1011
111
0
hit
14
00001110
0000
111
0
miss
They have the same index field 111, so the both the data goes into line number 7, but if we look closely, you can sport that the tag field does not match for a particular case because there is already an cache entry in the cache for that particular line with different tag or is empty. But when we access 190, we find a match for the index field 111 (both having tag field 10111110) so the entry for 190 is a hit. But for memory acceess 14 the tag field does not match and hence a miss.
191
10111111
1011
111
1
miss
88
01011000
0101
100
0
miss
190
10111110
1011
111
0
hit
14
00001110
0000
111
0
miss
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