Use this as your entity declaration 1ibrary IEEE use IEEE.STD_LOGIC1 164.ALL; 3

Question

Use this as your entity declaration 1ibrary IEEE use IEEE.STD_LOGIC1 164.ALL; 3 use IEEE.numeric_std.all; 5 Bentity ALU is 6 Egeneric 7 bit_depth : integer32) 8 Eport result A EQ_B A GT EB A_LT_B Error : out std logic vector (bit depth-1 downto 0): : out std logic:A equal B : out std logicA greater than B : out stdlogicA less than B : out std logic; : in std_logic_vector (bit_depth-1 downto 0) : in std logic vector (bit depth-1 downto 0) : in std_logic_vector (3 downto 0) 10 12 13 14 15 16 17 18 end ALU OpCode

Explanation / Answer

VHDL code for ALU is given here

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 17:37:40 10/12/2017

-- Design Name:

-- Module Name: ALU - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_unsigned.all;

--use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity ALU is

generic(bit_depth : integer:=32);

Port (

result : out STD_LOGIC_VECTOR (bit_depth-1 downto 0);

A_EQ_B : out STD_LOGIC;

A_GT_B : out STD_LOGIC;

A_LT_B : out STD_LOGIC;

Error : out STD_LOGIC;

A : in STD_LOGIC_VECTOR (bit_depth-1 downto 0);

B : in STD_LOGIC_VECTOR (bit_depth-1 downto 0);

OpCode : in STD_LOGIC_VECTOR (3 downto 0);

clock: in STD_LOGIC;

reset : in STD_LOGIC);

end ALU;

architecture Behavioral of ALU is

signal temp_out : STD_LOGIC_VECTOR(31 downto 0);

begin

ALU_Process: process(clock,reset)

begin

if(reset ='0') then

temp_out <= X"00000000";

elsif(rising_edge(clock)) then

case opcode is

when "0000" =>

temp_out <= X"00000000";

when "0001" =>

temp_out <= not A;

when "0010" =>

temp_out <= not B;

when "0011" =>

temp_out <= A + B;

when "0100" =>

temp_out <= A - B;

when "0101" =>

temp_out <= B - A;

when "0110" =>

temp_out <= A(27 downto 0)& A(31 downto 28);

when "0111" =>

temp_out <= A(3 downto 0)& A(31 downto 4);

when "1000" =>

temp_out <= B(29 downto 0)&B(31 downto 30);

when "1001" =>

temp_out <= B(1 downto 0)& B(31 downto 2);

when "1010" =>

temp_out(31 downto 0) <= A(31 downto 0);

-- for i in A'range loop

-- temp_out <= A(0);

-- end loop

--temp_out <= not A;

-- temp_out(0) <= A(31);

-- temp_out(1) <= A(30);

-- temp_out(2) <= A(29);

-- temp_out(3) <= A(28);

-- temp_out(4) <= A(27);

-- temp_out(5) <= A(26);

-- temp_out(6) <= A(25);

-- temp_out(7) <= A(23);

-- temp_out(8) <= A(31);

-- temp_out(9) <= A(30);

-- temp_out(10) <= A(29);

-- temp_out(11) <= A(28);

-- temp_out(12) <= A(27);

-- temp_out(13) <= A(26);

-- temp_out(6) <= A(25);

-- temp_out(7) <= A(23);

when "1011" =>

temp_out(31 downto 0) <= B(31 downto 0);

when "1100" =>

temp_out <= A and B;

when "1101" =>

temp_out <= A or B;

when "1110" =>

temp_out(31 downto 24) <= A(7 downto 0);

temp_out(23 downto 16) <= A(15 downto 8);

temp_out(15 downto 8) <= A(23 downto 16);

temp_out(7 downto 0) <= A(31 downto 24);

when others =>

temp_out <= A or B;

end case;

end if;

end process ALU_Process;

result <= temp_out;

A_EQ_B <= '1' when A=B else '0';

A_GT_B <= '1' when A>B else '0';

A_LT_B <= '1' when A<B else '0';

end Behavioral;

test bench for ALU design

--------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 18:52:36 10/12/2017

-- Design Name:

-- Module Name: D:/projects/Chegg_QAExpert/solutions/VHDL/ALU/tb_ALU.vhd

-- Project Name: ALU

-- Target Device:  

-- Tool versions:  

-- Description:

--

-- VHDL Test Bench Created by ISE for module: ALU

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

-- Notes:

-- This testbench has been automatically generated using types std_logic and

-- std_logic_vector for the ports of the unit under test. Xilinx recommends

-- that these types always be used for the top-level I/O of a design in order

-- to guarantee that the testbench will bind correctly to the post-implementation

-- simulation model.

--------------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY tb_ALU IS

END tb_ALU;

ARCHITECTURE behavior OF tb_ALU IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT ALU

PORT(

result : OUT std_logic_vector(31 downto 0);

A_EQ_B : OUT std_logic;

A_GT_B : OUT std_logic;

A_LT_B : OUT std_logic;

Error : OUT std_logic;

A : IN std_logic_vector(31 downto 0);

B : IN std_logic_vector(31 downto 0);

OpCode : IN std_logic_vector(3 downto 0);

clock : IN std_logic;

reset : IN std_logic

);

END COMPONENT;

  

--Inputs

signal A : std_logic_vector(31 downto 0) := (others => '0');

signal B : std_logic_vector(31 downto 0) := (others => '0');

signal OpCode : std_logic_vector(3 downto 0) := (others => '0');

signal clock : std_logic := '0';

signal reset : std_logic := '0';

--Outputs

signal result : std_logic_vector(31 downto 0);

signal A_EQ_B : std_logic;

signal A_GT_B : std_logic;

signal A_LT_B : std_logic;

signal Error : std_logic;

-- Clock period definitions

constant clock_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: ALU PORT MAP (

result => result,

A_EQ_B => A_EQ_B,

A_GT_B => A_GT_B,

A_LT_B => A_LT_B,

Error => Error,

A => A,

B => B,

OpCode => OpCode,

clock => clock,

reset => reset

);

-- Clock process definitions

-- clock_process :process

-- begin

-- clock <= '0';

-- wait for clock_period/2;

-- clock <= '1';

-- wait for clock_period/2;

-- end process;

-- Stimulus process

-- stim_proc: process

-- begin

-- -- hold reset state for 100 ns.

-- wait for 100 ns;

-- reset <= '0';

-- wait for clock_period*10;

-- -- insert stimulus here

-- A<=X"12345678";

-- B<=X"26789123";

-- end process;

RESET <= '0', '1' after 100 ns, '0' after 180 ns, '1' after 210 ns;

A<=X"12345678";

B<=X"26789123";

OpCode <= "0001" after 2000ns, "0010" after 4000ns, "0011" after 8000ns;

clockt: process

begin

clock <= '0';

wait for 5 ns;

clock <= '1';

wait for 5 ns;

--assert (NOW < 900 ns)

--report "Simulation completed successfully.";

end process clockt;

END;

---------------------------------------------------------

screenshot of simulated results

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