1. Load A in on cycle of clock with Xand left 2 cycles with W n = W n-1 = 0 ( L
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Question
1. Load A in on cycle of clock with Xand left 2 cycles with Wn = Wn-1 = 0 ( L = 1 --> 0 to load and shift with Dir = 0)
2. Load B with X and keep L = 1 for total 3 cycles. Reset = 0
3. Reset = 1 from 4th cycle and shift right A , B and SUM for 8 cycles. (L=0 to load and shift. Dir = 1 for right shift)
What is the end result of this operation? Show all your work and verify with a non-zero number.
A serial adder architecture shown below is to be used as a multiplier Shift register Sum bit D Q St Full Adder Carry-out Shift register i+1 Su Clock Clock D Q Parallel input Clock Shift register Clock ResetExplanation / Answer
(a) In 8 clock cycles, shift registers A & B will be able to provide inputs to Full adder block sequentially.. Hence after 8 clock cycles final sum and cout will be available.
(b) For the first set of bits (LSB) coming from shift registers A & B should be added by full adder with C0 = 0. Hence a reset (active Low) signal at D flip flop will do the required for the first bit addition with carry =0. For subsequent bits addition D Flip Flop will register previous carries.
(c) For substraction, either of the operands A/B needs to be 1's complemented or 2'complemented. Using extra NOT gates it can be achieved along with the full adder
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