This problem concerns the design of a 32-bit multiplier for floating point numbe

Question

This problem concerns the design of a 32-bit multiplier for floating point numbers (F1x251)* (F2X252) FX25 Assume that the numbers are initially in IEEE single precision format and the final result should be in the same format. The multiplier has two 32-bit floating point inputs and produce a 32-bit floating point output. You may consider positive numbers only and use round toward zero (truncate). You may also ignore the special cases. (0, NaN, inf, -inf) IEEE single precision format: bit bits bit gn Exponent Mantissa 32-bit 1 sign bit, 8 exponent bits, 23 fraction bits - bias = 127 For example: (58.25)10(1.1101001 2)2 Sign bit: 0 (positive) 8 bit exponent. (12745)-132=(10000100)2 23bit mantissa: 110 1001 0000 0000 0000 0000 23 bits 110 1001 0000 0000 0000 0000 1 bit 8 bits 1 100 0010 0 Sign Exponent Fraction

Explanation / Answer

module fpadd(a,b,out,e1,e2,exy,s1,s2,sr,sign,m1,m2,mx,my,mxy,mxy2);
input[31:0]a,b;

output reg [31:0]out;
output reg [7:0]e1,e2,exy;
output reg s1,s2,sr,sign;
output reg [23:0]m1,m2,mx,my;
output reg [24:0]mxy,mxy2;
reg [7:0] diff,i,x;
always @ (a or b)
begin
s1=a[31];
s2=b[31];
e1=a[30:23];
e2=b[30:23];
m1[23]=1'b1;
m2[23]=1'b1;
m1[22:0]=a[22:0];
m2[22:0]=b[22:0];

if(e1==e2)
begin
mx=m1;
my=m2;
exy=e1+1'b1;
sign=s1;
end
else if(e1>e2)
begin
diff=e1-e2;
mx=m1;
my=m2>>diff;
exy=e1+1'b1;
sign=s1;
end
else
begin
diff=e2-e1;

mx=m2;
my=m1>>diff;
exy=e2+1'b1;
sign=s2;
end

sr=s1^s2;
if(sr==0)
begin
mxy=mx+my;
sign=s1;
end
else
begin
mxy=mx-my;
end
mxy2=mxy;

if(s1==0 && s2==0)
sign=1'b0;
else if (s1==1 && s2==1)
sign=1'b1;
else if (s1==0 && s2==1)
begin
if(e1<e2 || ((e1==e2) && (m1<m2)))
sign=1'b1;
else
sign=1'b0;
end
else
begin
if(e1<e2 || ((e1==e2) && (m1<m2)))
sign=1'b0;
else
sign=1'b1;
end

for(i=0;i<24;i=i+1)

if (mxy[24]==0)
begin
mxy = mxy << 1;
exy = exy - 1;
end

if (mxy[23:0]==24'b0000000000000000000000000)
begin
out=32'b00000000000000000000000000000000;
end
else
begin
out= {sign,exy,mxy[23:1]};
end
end

endmodule

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