FILE: Project.v //Boolean Function 1 module TruthTable3(input a, input b, input

Question

FILE: Project.v

//Boolean Function 1
module TruthTable3(input a, input b, input c, output y);
//write your code here
endmodule

//Boolean Function 2
module TruthTable4(input a, input b, input c, input d, output y);
//write your code here
endmodule

//Absolute Value
module absolute(input [31:0] x,
output reg [31:0] y);
//write your code here
endmodule

//8x1 32-bit Multiplexer
module mux32(input [7:0][31:0] x,
input [2:0] sel,
output reg [31:0] y);
//write your code here
endmodule

//32-bit adder
//To get all scores, you cannot use arithmetic operators in this module.
module adder(input [31:0] x,
input [31:0] y,
input ci,
output reg co,
output reg [31:0] s);
//write your code here
endmodule

//32-bit shifter
//To get all scores, you cannot use shift operators in this module.
module shifter(input [31:0] x,
input [4:0] c,
input [1:0] op,
output reg [31:0] y);
//write your code here
endmodule

//32-bit ALU
//To get all scores, you cannot use arithmetic operators in this module.
module ALU(
       input [31:0] a,
       input [31:0] b,
       input [2:0] op,
       output reg [31:0] s);
//write your code here
endmodule

Introduction The purpose of this project is to become more familiar with the design of digital circuits and to implement digital circuits in Verilog. You will do this by implementing a series of digital circuits, i.e., "modules" in Verilog.

Explanation / Answer

FIRST FOUR QUESTIONS ANSWERED

//Boolean Function 1

module TruthTable3(input a, input b, input c, output y);

//the equation obtained is implemented as code here

assign y=(a&b)|c;

endmodule

//Boolean Function 2

module TruthTable4(input a, input b, input c, input d, output y);

//the equation obtained is implemented as code here

assign y=(a&b)|(c&d);

endmodule

//Absolute Value

module absolute(input reg[31:0] x,

output reg [31:0] y);

// absolute value is inverted

always @* begin

// if 31th bit is 1 then invert input

if (x[31] == 1'b1) begin

y = -x;

end

else begin

// if 31th bit is not 1 then dont invert

y = x;

end

end

endmodule

//8x1 32-bit Multiplexer

module mux32(input [7:0][31:0] x,

input [2:0] sel,

output reg [31:0] y);

//write your code here

always @( sel or x )

//CASE STATEMENT USED TO SELECT AN OUTPUT

begin

case( sel )

0 : y = x[0];

1 : y = x[1];

2 : y = x[2];

3 : y = x[3];

4 : y = x[4];

5 : y = x[5];

6 : y = x[6];

7 : y = x[7];

endcase

end

endmodule

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