(Note that each member in the group should do this individually) 1) Read the DE2
ID: 2290936 • Letter: #
Question
(Note that each member in the group should do this individually) 1) Read the DE2-115 User Manual about the PS/2 Serial Port from page 55 to 56. Optional: Read any other open source documentation you deem necessary on the keyboard interfacing and on the PS/2 protocol Pressing a key sends a transmission of 11 bits, 8 of which are data bits in the following format (see figure below) Keyboard Clk Keyboard Data Start bit 0 arity Stop it bit 1 One 11 bit Transmission with 8 data bits Figure 1: Keyboard Transmission Some keys transmit two transmissions for a total of 22 bits, 16 bits which are data bits. Keys such as the arrow keys have two transmissions. The following codes that are sent for the keys when pressed are show below in the figure. The keys shown in figure 2 transmit the following hexadecimal codes for a total of 8 or 16 data bits. Also note that the keyboard clock only oscillates when it is transmitting data, else the keyboard clock is not oscillating when not transmitting.Explanation / Answer
A couple of assumptions are made due to lack of information which are listed below:
1. There exists output modules that take BCD inputs and drive 7 segment displays with the ability to display 0-9 and A-F.
2. There exists 22 bit shift register modules with serial in serial out and parallel out signals.
3. There exists a predefined module to check parity.
4. The pseudo code is in VHDL flavour.
Following is the pseudo code with "//" representing comments.
Code begins from next line
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Include all libraries for using signals.
define entity PS2 controller
define input signals clock and data. : clk and data // Initializing input
define system clock to drive the 7 segment display and multiplexer.: sm_clk , seven_out // Output signals
define output signals to multiplex and show received bytes on 7 segment display.
end entity PS2 controller
architecture of entity PS2 controller
define a signal to count 22 numbers (5 bit long integer) : count
define intermediate signal out_latch to control when the received signal is sent to decoder block. (1 bit long): out_latch
define intermediate signal to store output of shift register (22 bit long): shift_reg_out
define signal to store latched output (22 bit long): latched_out
define signal to store if received data is one byte or two byte long(1 bit long): data_len_flag
define signal to flag a successfull reception : success_flag
call the components "seven_segment_decoder " and "22_bit_shift_reg"
begin architecture
instantiate the 7 segment decoder and multiplexer block. Map the system clock to drive the multiplexer.
instantiate 22 bit shift register. Map its clock to clk and data in to data signals. Map output signal to
shift_reg_out
begin process to check for clock by the keyboard and test the input
if(clk'event and clk = '1') // Rising edge of clock
count = count + 1
if(count == 11 and shift_reg_out != E0)
data_len_flag = 0
count = 0
latched_out = shif_reg_out
success_flag = 1
els if (count == 11 and shift_reg_out == E0)
data_len_flag = 1
els if(count == 22)
count = 0
latched_out = shift_reg_out
success_flag = 1
end process
begin process to extract message to be displayed from 22 bit latched message
if(success_flag == 1)
if(data_len_flag == 0)
if(parity_check = latched_output(21))
output_to_multiplexer = latched_ouput(20 downto 13)+"00000000"
if(data_len_flag == 1)
if(parity_check = latched_output(21))
output_to_multiplexer = latched_ouput(20 downto 13)+ latched_ouput(8 downto 1)
end process
end architecture
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Note: Due to lack of time the instantiation of parity check module and its interface is not given in the code. Assume those signals appropriately.
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