The circuit below is called an NP-Domino circuit It is a cascade of a number of

Question

The circuit below is called an NP-Domino circuit It is a cascade of a number of dynamic logic stages. a) Explain the functionality of the NP-Domino circuit. State why you no longer need inverters etween each stage b) What are the advantages and disadvantages of using NP-Domino versus conventional omino logic when gates are cascaded (state 2 advantages and 2 disadvantages) What is the switching threshold(s) (VM) of NP-Domino circuit? ck clk .c to futher P blocks inputs stable during N-logicP-logicN-logic other P blocks other N blocks

Explanation / Answer

a) Domino logic is a CMOS-based evolution of the dynamic logic techniques based on either PMOS or NMOS transistors.It allows a rail-to-rail logic swing. It was developed to speed up circuits.

we are using Domino logic instead of inverter because , a problem arises when cascading one gate to the next. The precharge "1" state of the first gate may cause the second gate to discharge prematurely, before the first gate has reached its correct state. This uses up the "precharge" of the second gate, which cannot be restored until the next clock cycle, so there is no recovery from this error.

b) Advantages : In order to cascade dynamic logic gates, one solution is Domino Logic, which inserts an ordinary static inverter between stages. While this might seem to defeat the point of dynamic logic, since the inverter has a pFET (one of the main goals of Dynamic Logic is to avoid pFETs where possible, due to speed), there are two reasons it works well. First, there is no fanout to multiple pFETs;

Disadvantages :They have smaller areas than conventional CMOS logic (as does all Dynamic Logic The dynamic gate connects to exactly one inverter, so the gate is still very fast.  

c) A variable treshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits.this technique enhances circuit evaluation speed by 60% while reducing power dissipation by 35% as compared to SD circuit.

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